implements proper target XML generation incl. CSRs
This commit is contained in:
parent
de79adc50d
commit
6305efa7c2
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@ -20,6 +20,7 @@ set(LIB_SOURCES
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src/iss/arch/tgc5c.cpp
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src/vm/interp/vm_tgc5c.cpp
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src/vm/fp_functions.cpp
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src/iss/debugger/csr_names.cpp
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src/iss/semihosting/semihosting.cpp
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)
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File diff suppressed because it is too large
Load Diff
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@ -30,8 +30,8 @@
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*
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*******************************************************************************/
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#ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#ifndef _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#define _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#include "iss/arch_if.h"
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#include <iss/arch/traits.h>
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@ -39,6 +39,8 @@
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#include <iss/iss.h>
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#include <array>
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#include <iostream>
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#include <fstream>
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#include <memory>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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@ -48,6 +50,10 @@
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namespace iss {
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namespace debugger {
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char const* const get_csr_name(unsigned);
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constexpr auto csr_offset = 100U;
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using namespace iss::arch;
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using namespace iss::debugger;
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@ -129,11 +135,21 @@ public:
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protected:
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static inline constexpr addr_t map_addr(const addr_t& i) { return i; }
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std::string csr_xml;
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iss::arch_if* core;
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rp_thread_ref thread_idx;
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};
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template <typename ARCH>
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typename std::enable_if<iss::arch::traits<ARCH>::FLEN!=0, unsigned>::type get_f0_offset() {
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return iss::arch::traits<ARCH>::F0;
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}
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template <typename ARCH>
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typename std::enable_if<iss::arch::traits<ARCH>::FLEN==0, unsigned>::type get_f0_offset() {
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return 0;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
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thread_idx = thread;
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return Ok;
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@ -175,12 +191,29 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
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template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
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CPPLOG(TRACE) << "reading target registers";
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// return idx<0?:;
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data.clear();
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avail.clear();
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const uint8_t* reg_base = core->get_regs_base_ptr();
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auto start_reg = arch::traits<ARCH>::X0;
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for(size_t reg_no = start_reg; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
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for(size_t i = 0; i < 33; ++i) {
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if(i < arch::traits<ARCH>::RFS || i == arch::traits<ARCH>::PC) {
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auto reg_no = i<32? start_reg + i: arch::traits<ARCH>::PC;
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unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
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data.push_back(*(reg_base + offset + j));
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avail.push_back(0xff);
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}
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} else {
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
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data.push_back(0);
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avail.push_back(0);
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}
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}
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}
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if(iss::arch::traits<ARCH>::FLEN > 0) {
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auto fstart_reg = get_f0_offset<ARCH>();
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for(size_t i = 0; i < 32; ++i) {
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auto reg_no = fstart_reg + i;
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
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unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
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for(size_t j = 0; j < reg_width; ++j) {
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@ -188,21 +221,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::
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avail.push_back(0xff);
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}
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}
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// work around fill with F type registers
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// if (arch::traits<ARCH>::NUM_REGS < 65) {
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// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
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// for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
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// for (size_t j = 0; j < reg_width; ++j) {
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// data.push_back(0x0);
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// avail.push_back(0x00);
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// }
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// // if(arch::traits<ARCH>::XLEN < 64)
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// // for(unsigned j=0; j<4; ++j){
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// // data.push_back(0x0);
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// // avail.push_back(0x00);
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// // }
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// }
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// }
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}
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return Ok;
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}
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@ -210,25 +229,25 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
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auto start_reg = arch::traits<ARCH>::X0;
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auto* reg_base = core->get_regs_base_ptr();
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auto iter = data.data();
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bool e_ext = arch::traits<ARCH>::PC < 32;
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for(size_t reg_no = 0; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
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if(e_ext && reg_no > 15) {
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if(reg_no == 32) {
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
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auto iter_end = data.data()+data.size();
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for(size_t i = 0; i < 33 && iter < iter_end; ++i) {
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auto reg_width = arch::traits<ARCH>::XLEN / 8;
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if(i < arch::traits<ARCH>::RFS) {
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auto offset = traits<ARCH>::reg_byte_offsets[start_reg + i];
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std::copy(iter, iter + reg_width, reg_base+offset);
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} else if(i == 32) {
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auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
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std::copy(iter, iter + reg_width, reg_base);
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} else {
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const uint64_t zero_val = 0;
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
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auto iter = (uint8_t*)&zero_val;
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std::copy(iter, iter + reg_width, reg_base);
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std::copy(iter, iter + reg_width, reg_base+offset);
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}
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} else {
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
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std::copy(iter, iter + reg_width, reg_base);
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iter += 4;
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reg_base += offset;
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iter += reg_width;
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}
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if(iss::arch::traits<ARCH>::FLEN > 0) {
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auto fstart_reg = get_f0_offset<ARCH>();
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auto reg_width = arch::traits<ARCH>::FLEN / 8;
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for(size_t i = 0; i < 32 && iter < iter_end; ++i) {
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unsigned offset = traits<ARCH>::reg_byte_offsets[fstart_reg + i];
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std::copy(iter, iter + reg_width, reg_base+offset);
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iter += reg_width;
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}
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}
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return Ok;
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@ -236,7 +255,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
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if(reg_no < 65) {
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if(reg_no <csr_offset) {
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// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
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// arch::traits<ARCH>::reg_e>(reg_no))/8;
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auto* reg_base = core->get_regs_base_ptr();
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@ -247,23 +266,24 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
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std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
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std::fill(avail.begin(), avail.end(), 0xff);
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} else {
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - csr_offset);
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data.resize(sizeof(typename traits<ARCH>::reg_t));
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avail.resize(sizeof(typename traits<ARCH>::reg_t));
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std::fill(avail.begin(), avail.end(), 0xff);
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core->read(a, data.size(), data.data());
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std::fill(avail.begin(), avail.end(), 0xff);
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}
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return data.size() > 0 ? Ok : Err;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
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if(reg_no < 65) {
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if(reg_no < csr_offset) {
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auto* reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
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std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
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} else {
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - csr_offset);
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core->write(a, data.size(), data.data());
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}
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return Ok;
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@ -276,7 +296,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t ad
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
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auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
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auto a = map_addr({iss::access_type::DEBUG_WRITE, iss::address_type::VIRTUAL, 0, addr});
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auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
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return srv->execute_syncronized(f);
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}
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@ -369,93 +389,55 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
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const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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"<target><architecture>riscv:rv32</architecture>"
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//" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
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//" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
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//" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
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//" </feature>\n"
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"</target>"};
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out_buf = res;
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if(!csr_xml.size()) {
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std::ostringstream oss;
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oss << "<?xml version=\"1.0\"?><!DOCTYPE feature SYSTEM \"gdb-target.dtd\"><target version=\"1.0\">\n";
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if(iss::arch::traits<ARCH>::XLEN == 32)
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oss << "<architecture>riscv:rv32</architecture>\n";
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else if(iss::arch::traits<ARCH>::XLEN == 64)
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oss << " <architectureriscv:rv64</architecture>\n";
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oss << " <feature name=\"org.gnu.gdb.riscv.cpu\">\n";
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auto reg_base_num = iss::arch::traits<ARCH>::X0;
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for(auto i = 0U; i<iss::arch::traits<ARCH>::RFS; ++i) {
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oss << " <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\"int\" regnum=\"" << i << "\"/>\n";
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}
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oss << " <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC] << "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
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oss << " </feature>\n";
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if(iss::arch::traits<ARCH>::FLEN > 0) {
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oss << " <feature name=\"org.gnu.gdb.riscv.fpu\">\n";
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auto reg_base_num = get_f0_offset<ARCH>();
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auto type = iss::arch::traits<ARCH>::FLEN==32?"ieee_single":"riscv_double";
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for(auto i = 0U; i<32; ++i) {
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oss << " <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\""<<type<<"\" regnum=\"" << i+33 << "\"/>\n";
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}
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oss << " <reg name=\"fcsr\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"103\" type int/>\n";
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oss << " <reg name=\"fflags\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"101\" type int/>\n";
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oss << " <reg name=\"frm\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"102\" type int/>\n";
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oss << " </feature>\n";
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}
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oss << " <feature name=\"org.gnu.gdb.riscv.csr\">\n";
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std::vector<uint8_t> data;
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std::vector<uint8_t> avail;
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data.resize(sizeof(typename traits<ARCH>::reg_t));
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avail.resize(sizeof(typename traits<ARCH>::reg_t));
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for(auto i = 0U; i<4096; ++i) {
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, i);
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std::fill(avail.begin(), avail.end(), 0xff);
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auto res = core->read(a, data.size(), data.data());
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if(res == iss::Ok) {
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oss << " <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
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}
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}
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oss << " </feature>\n";
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oss << "</target>\n";
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csr_xml = oss.str();
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std::ofstream ofs("target.xml");
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ofs<<csr_xml;
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}
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out_buf = csr_xml;
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return Ok;
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}
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/*
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*
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<?xml version="1.0"?>
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target>
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<architecture>riscv:rv32</architecture>
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<feature name="org.gnu.gdb.riscv.rv32i">
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<reg name="x0" bitsize="32" group="general"/>
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<reg name="x1" bitsize="32" group="general"/>
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<reg name="x2" bitsize="32" group="general"/>
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<reg name="x3" bitsize="32" group="general"/>
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<reg name="x4" bitsize="32" group="general"/>
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<reg name="x5" bitsize="32" group="general"/>
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<reg name="x6" bitsize="32" group="general"/>
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<reg name="x7" bitsize="32" group="general"/>
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<reg name="x8" bitsize="32" group="general"/>
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<reg name="x9" bitsize="32" group="general"/>
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<reg name="x10" bitsize="32" group="general"/>
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<reg name="x11" bitsize="32" group="general"/>
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<reg name="x12" bitsize="32" group="general"/>
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<reg name="x13" bitsize="32" group="general"/>
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<reg name="x14" bitsize="32" group="general"/>
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<reg name="x15" bitsize="32" group="general"/>
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<reg name="x16" bitsize="32" group="general"/>
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<reg name="x17" bitsize="32" group="general"/>
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<reg name="x18" bitsize="32" group="general"/>
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<reg name="x19" bitsize="32" group="general"/>
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<reg name="x20" bitsize="32" group="general"/>
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<reg name="x21" bitsize="32" group="general"/>
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<reg name="x22" bitsize="32" group="general"/>
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<reg name="x23" bitsize="32" group="general"/>
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<reg name="x24" bitsize="32" group="general"/>
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<reg name="x25" bitsize="32" group="general"/>
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<reg name="x26" bitsize="32" group="general"/>
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<reg name="x27" bitsize="32" group="general"/>
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<reg name="x28" bitsize="32" group="general"/>
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<reg name="x29" bitsize="32" group="general"/>
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<reg name="x30" bitsize="32" group="general"/>
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<reg name="x31" bitsize="32" group="general"/>
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</feature>
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||||
</target>
|
||||
|
||||
*/
|
||||
} // namespace debugger
|
||||
} // namespace iss
|
||||
|
||||
#endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */
|
||||
#endif /* _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue