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fixes CSR to match latest fast interrupts spec

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Eyck Jentzsch
2023-01-20 16:21:04 +01:00
parent 65dca13b42
commit 62c118e501
3 changed files with 1 additions and 8 deletions
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src/iss/arch/riscv_hart_common.h
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@ -115,10 +115,9 @@ enum riscv_csr {
mip = 0x344,
mxnti = 0x345, //CLIC
mintstatus = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
mintthresh = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
mintthresh = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
mclicbase = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
// Physical Memory Protection
pmpcfg0 = 0x3A0,
pmpcfg1 = 0x3A1,