corrects softfloat to comply with RVD ACT
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4c0d1c75aa
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@ -203,8 +203,8 @@ uint32_t fclass_s(uint32_t v1) {
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uA.f = a;
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uA.f = a;
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uiA = uA.ui;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF32UI(uiA) == 0xFF;
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bool infOrNaN = expF32UI(uiA) == 0xFF;
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uint_fast16_t subnormalOrZero = expF32UI(uiA) == 0;
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bool subnormalOrZero = expF32UI(uiA) == 0;
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bool sign = signF32UI(uiA);
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bool sign = signF32UI(uiA);
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bool fracZero = fracF32UI(uiA) == 0;
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bool fracZero = fracF32UI(uiA) == 0;
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bool isNaN = isNaNF32UI(uiA);
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bool isNaN = isNaNF32UI(uiA);
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@ -217,9 +217,13 @@ uint32_t fclass_s(uint32_t v1) {
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}
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}
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uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
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uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
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bool isNan = isNaNF64UI(v1);
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bool isSNaN = softfloat_isSigNaNF64UI(v1);
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softfloat_roundingMode = rmm_map.at(mode);
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softfloat_roundingMode = rmm_map.at(mode);
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bool nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI;
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softfloat_exceptionFlags = 0;
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if(nan) {
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if(isNan) {
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if(isSNaN)
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softfloat_raiseFlags(softfloat_flag_invalid);
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return defaultNaNF32UI;
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return defaultNaNF32UI;
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} else {
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} else {
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float32_t res = f64_to_f32(float64_t{v1});
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float32_t res = f64_to_f32(float64_t{v1});
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@ -228,11 +232,11 @@ uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
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}
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}
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uint64_t fconv_f2d(uint32_t v1, uint8_t mode) {
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uint64_t fconv_f2d(uint32_t v1, uint8_t mode) {
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bool nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI;
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bool infOrNaN = expF32UI(v1) == 0xFF;
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if(nan) {
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bool subnormalOrZero = expF32UI(v1) == 0;
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if(infOrNaN || subnormalOrZero) {
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return defaultNaNF64UI;
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return defaultNaNF64UI;
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} else {
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} else {
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softfloat_roundingMode = rmm_map.at(mode);
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float64_t res = f32_to_f64(float32_t{v1});
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float64_t res = f32_to_f64(float32_t{v1});
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return res.v;
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return res.v;
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}
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}
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@ -312,22 +316,23 @@ uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
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}
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}
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uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
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uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
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float64_t v1f{v1};
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float64_t v1f{v1};
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softfloat_exceptionFlags = 0;
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softfloat_exceptionFlags = 0;
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float64_t r;
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float64_t r;
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switch(op) {
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switch(op) {
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case 0: { // l->d, fp to int32
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case 0: { // l from d
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int64_t res = f64_to_i64(v1f, rmm_map.at(mode), true);
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int64_t res = f64_to_i64(v1f, rmm_map.at(mode), true);
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return (uint64_t)res;
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return (uint64_t)res;
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}
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}
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case 1: { // lu->s
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case 1: { // lu from d
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uint64_t res = f64_to_ui64(v1f, rmm_map.at(mode), true);
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uint64_t res = f64_to_ui64(v1f, rmm_map.at(mode), true);
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return res;
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return res;
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}
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}
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case 2: // s->l
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case 2: // d from l
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r = i64_to_f64(v1);
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r = i64_to_f64(v1);
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return r.v;
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return r.v;
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case 3: // s->lu
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case 3: // d from lu
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r = ui64_to_f64(v1);
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r = ui64_to_f64(v1);
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return r.v;
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return r.v;
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}
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}
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@ -335,12 +340,24 @@ uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
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}
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}
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uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
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uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
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// op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
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uint64_t F64_SIGN = 1ULL << 63;
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switch(op) {
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case 0: // FMADD_D
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break;
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case 1: // FMSUB_D
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v3 ^= F64_SIGN;
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break;
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case 2: // FNMADD_D
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v1 ^= F64_SIGN;
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v3 ^= F64_SIGN;
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break;
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case 3: // FNMSUB_D
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v1 ^= F64_SIGN;
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break;
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}
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softfloat_roundingMode = rmm_map.at(mode);
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softfloat_roundingMode = rmm_map.at(mode);
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softfloat_exceptionFlags = 0;
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softfloat_exceptionFlags = 0;
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float64_t res = softfloat_mulAddF64(v1, v2, v3, op & 0x1);
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float64_t res = softfloat_mulAddF64(v1, v2, v3, 0);
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if(op > 1)
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res.v ^= 1ULL << 63;
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return res.v;
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return res.v;
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}
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}
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@ -376,8 +393,8 @@ uint64_t fclass_d(uint64_t v1) {
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uA.f = a;
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uA.f = a;
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uiA = uA.ui;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF64UI(uiA) == 0x7FF;
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bool infOrNaN = expF64UI(uiA) == 0x7FF;
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uint_fast16_t subnormalOrZero = expF64UI(uiA) == 0;
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bool subnormalOrZero = expF64UI(uiA) == 0;
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bool sign = signF64UI(uiA);
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bool sign = signF64UI(uiA);
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bool fracZero = fracF64UI(uiA) == 0;
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bool fracZero = fracF64UI(uiA) == 0;
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bool isNaN = isNaNF64UI(uiA);
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bool isNaN = isNaNF64UI(uiA);
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