DBT-RISE/DBT-RISE-TGC
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Fixed validation errors in core dsl files.

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Eyck Jentzsch
2018-05-09 12:14:59 +02:00
parent 19b660962b
commit 5b6dc36c9d
8 changed files with 528 additions and 327 deletions
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4
riscv/gen_input/RV32D.core_desc
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@@ -11,7 +11,7 @@ InsructionSet RV32D extends RV32IBase{
FLD {
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
args_disass:"f%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s + imm;
val res[64] <= MEM[offs]{64};
if(FLEN==64)
F[rd] <= res;
@@ -23,7 +23,7 @@ InsructionSet RV32D extends RV32IBase{
FSD {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
args_disass:"f%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{64}<=F[rs2]{64};
}
FMADD.D {