Refoctored to to move SystemC wrapper into riscv library
This commit is contained in:
161
riscv/incl/sysc/core_complex.h
Normal file
161
riscv/incl/sysc/core_complex.h
Normal file
@ -0,0 +1,161 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
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||||
*
|
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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||||
* may be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#ifndef _SYSC_SIFIVE_FE310_H_
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#define _SYSC_SIFIVE_FE310_H_
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#include "scc/initiator_mixin.h"
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#include "scc/traceable.h"
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#include "scc/utilities.h"
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#include "scv4tlm/tlm_rec_initiator_socket.h"
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#include <cci_configuration>
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#include <tlm>
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#include <tlm_utils/tlm_quantumkeeper.h>
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#include <util/range_lut.h>
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class scv_tr_db;
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class scv_tr_stream;
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struct _scv_tr_generator_default_data;
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template <class T_begin, class T_end> class scv_tr_generator;
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namespace iss {
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class vm_if;
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namespace arch {
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template <typename BASE> class riscv_hart_msu_vp;
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}
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namespace debugger {
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class target_adapter_if;
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}
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}
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namespace sysc {
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class tlm_dmi_ext : public tlm::tlm_dmi {
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public:
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bool operator==(const tlm_dmi_ext &o) const {
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return this->get_granted_access() == o.get_granted_access() &&
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this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
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}
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bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
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};
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namespace SiFive {
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class core_wrapper;
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class core_complex : public sc_core::sc_module, public scc::traceable {
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public:
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SC_HAS_PROCESS(core_complex);// NOLINT
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scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator;
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sc_core::sc_in<sc_core::sc_time> clk_i;
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sc_core::sc_in<bool> rst_i;
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sc_core::sc_in<bool> global_irq_i;
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sc_core::sc_in<bool> timer_irq_i;
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sc_core::sc_in<bool> sw_irq_i;
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sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
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cci::cci_param<std::string> elf_file;
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cci::cci_param<bool> enable_disass;
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cci::cci_param<uint64_t> reset_address;
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cci::cci_param<unsigned short> gdb_server_port;
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cci::cci_param<bool> dump_ir;
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core_complex(sc_core::sc_module_name name);
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~core_complex();
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inline void sync(uint64_t cycle) {
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auto time = curr_clk * (cycle - last_sync_cycle);
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quantum_keeper.inc(time);
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if (quantum_keeper.need_sync()) {
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wait(quantum_keeper.get_local_time());
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quantum_keeper.reset();
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}
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last_sync_cycle = cycle;
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}
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bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
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bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
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bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
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bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
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void trace(sc_core::sc_trace_file *trf) const override;
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void disass_output(uint64_t pc, const std::string instr);
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protected:
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void before_end_of_elaboration();
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void start_of_simulation();
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void run();
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void clk_cb();
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void rst_cb();
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void sw_irq_cb();
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void timer_irq_cb();
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void global_irq_cb();
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uint64_t last_sync_cycle = 0;
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util::range_lut<tlm_dmi_ext> read_lut, write_lut;
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tlm_utils::tlm_quantumkeeper quantum_keeper;
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std::vector<uint8_t> write_buf;
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std::unique_ptr<core_wrapper> cpu;
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std::unique_ptr<iss::vm_if> vm;
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sc_core::sc_time curr_clk;
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iss::debugger::target_adapter_if *tgt_adapter;
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#ifdef WITH_SCV
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//! transaction recording database
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scv_tr_db *m_db;
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//! blocking transaction recording stream handle
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scv_tr_stream *stream_handle;
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//! transaction generator handle for blocking transactions
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scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
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scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
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scv_tr_handle tr_handle;
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#endif
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};
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} /* namespace SiFive */
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} /* namespace sysc */
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#endif /* _SYSC_SIFIVE_FE310_H_ */
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@ -12,6 +12,10 @@ set(LIB_SOURCES
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plugin/instruction_count.cpp
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plugin/cycle_estimate.cpp)
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if(SystemC_FOUND)
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set(LIB_SOURCES ${LIB_SOURCES} sysc/core_complex.cpp)
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endif()
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set(APP_HEADERS )
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set(APP_SOURCES main.cpp)
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@ -28,6 +32,18 @@ set_target_properties(${LIBRARY_NAME} PROPERTIES
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PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
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)
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if(SystemC_FOUND)
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add_definitions(-DWITH_SYSTEMC)
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include_directories(${SystemC_INCLUDE_DIRS})
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include_directories(${CCI_INCLUDE_DIRS})
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if(SCV_FOUND)
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add_definitions(-DWITH_SCV)
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include_directories(${SCV_INCLUDE_DIRS})
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endif()
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endif()
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# This is a make target, so you can do a "make riscv-sc"
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set(APPLICATION_NAME riscv-sim)
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483
riscv/src/sysc/core_complex.cpp
Normal file
483
riscv/src/sysc/core_complex.cpp
Normal file
@ -0,0 +1,483 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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||||
*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include "sysc/core_complex.h"
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#include "iss/arch/riscv_hart_msu_vp.h"
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#include "iss/arch/rv32imac.h"
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#include "iss/debugger/encoderdecoder.h"
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#include "iss/debugger/gdb_session.h"
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#include "iss/debugger/server.h"
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#include "iss/debugger/target_adapter_if.h"
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#include "iss/iss.h"
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#include "iss/vm_types.h"
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#include "scc/report.h"
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#include <sstream>
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#include <iostream>
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#ifdef WITH_SCV
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#include <array>
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#include <scv.h>
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#endif
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namespace sysc {
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namespace SiFive {
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using namespace std;
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using namespace iss;
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using namespace logging;
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using namespace sc_core;
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namespace {
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iss::debugger::encoder_decoder encdec;
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}
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namespace {
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std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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std::array<const char*, 16> trap_str = { {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store/AMO address misaligned",
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"Store/AMO access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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"Reserved",
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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"Reserved",
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"Store/AMO page fault"
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} };
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std::array<const char*, 12> irq_str = { {
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"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
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"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
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"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
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}
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class core_wrapper : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac> {
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public:
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using core_type = arch::rv32imac;
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using base_type = arch::riscv_hart_msu_vp<arch::rv32imac>;
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using phys_addr_t = typename arch::traits<arch::rv32imac>::phys_addr_t;
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core_wrapper(core_complex *owner)
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: owner(owner) {}
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uint32_t get_mode() { return this->reg.machine_state; }
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inline void set_interrupt_execution(bool v) { this->interrupt_sim = v; }
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inline bool get_interrupt_execution() { return this->interrupt_sim; }
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base_type::hart_state<base_type::reg_t> &get_state() { return this->state; }
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void notify_phase(exec_phase p) override {
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if (p == ISTART) owner->sync(this->reg.icount + cycle_offset);
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}
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sync_type needed_sync() const override { return PRE_SYNC; }
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void disass_output(uint64_t pc, const std::string instr) override {
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if (INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
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std::stringstream s;
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s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
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<< std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
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Log<Output2FILE<disass>>().get(INFO, "disass")
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<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
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<< std::setfill(' ') << std::left << instr << s.str();
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}
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owner->disass_output(pc, instr);
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};
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status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
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if (addr.access && access_type::DEBUG)
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return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
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else {
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return owner->read_mem(addr.val, length, data, addr.access && access_type::FETCH) ? Ok : Err;
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}
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}
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status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
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if (addr.access && access_type::DEBUG)
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return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
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else {
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auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
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// clear MTIP on mtimecmp write
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if (addr.val == 0x2004000) {
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reg_t val;
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this->read_csr(arch::mip, val);
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if (val & (1ULL << 7)) this->write_csr(arch::mip, val & ~(1ULL << 7));
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}
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return res;
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}
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}
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void wait_until(uint64_t flags) override {
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SCDEBUG(owner->name()) << "Sleeping until interrupt";
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do {
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wait(wfi_evt);
|
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} while (this->reg.pending_trap == 0);
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base_type::wait_until(flags);
|
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}
|
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void local_irq(short id, bool value) {
|
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base_type::reg_t mask = 0;
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switch (id) {
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case 16: // SW
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mask = 1 << 3;
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break;
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case 17: // timer
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mask = 1 << 7;
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break;
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case 18: // external
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mask = 1 << 11;
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break;
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default:
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/* do nothing*/
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break;
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}
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if (value) {
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this->csr[arch::mip] |= mask;
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wfi_evt.notify();
|
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} else
|
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this->csr[arch::mip] &= ~mask;
|
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this->check_interrupt();
|
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}
|
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|
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private:
|
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core_complex *const owner;
|
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sc_event wfi_evt;
|
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};
|
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|
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int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func df,
|
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debugger::target_adapter_if *tgt_adapter) {
|
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if (argc > 1) {
|
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if (strcasecmp(argv[1], "print_time") == 0) {
|
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std::string t = sc_time_stamp().to_string();
|
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of(t.c_str());
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std::array<char, 64> buf;
|
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encdec.enc_string(t.c_str(), buf.data(), 63);
|
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df(buf.data());
|
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return Ok;
|
||||
} else if (strcasecmp(argv[1], "break") == 0) {
|
||||
sc_time t;
|
||||
if (argc == 4) {
|
||||
t = scc::parse_from_string(argv[2], argv[3]);
|
||||
} else if (argc == 3) {
|
||||
t = scc::parse_from_string(argv[2]);
|
||||
} else
|
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return Err;
|
||||
// no check needed as it is only called if debug server is active
|
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tgt_adapter->add_break_condition([t]() -> unsigned {
|
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SCTRACE() << "Checking condition at " << sc_time_stamp();
|
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return sc_time_stamp() >= t ? std::numeric_limits<unsigned>::max() : 0;
|
||||
});
|
||||
return Ok;
|
||||
}
|
||||
return Err;
|
||||
}
|
||||
return Err;
|
||||
}
|
||||
|
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core_complex::core_complex(sc_module_name name)
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: sc_module(name)
|
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, NAMED(initiator)
|
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, NAMED(clk_i)
|
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, NAMED(rst_i)
|
||||
, NAMED(global_irq_i)
|
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, NAMED(timer_irq_i)
|
||||
, NAMED(local_irq_i, 16)
|
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, NAMED(elf_file, "")
|
||||
, NAMED(enable_disass, false)
|
||||
, NAMED(reset_address, 0ULL)
|
||||
, NAMED(gdb_server_port, 0)
|
||||
, NAMED(dump_ir, false)
|
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, read_lut(tlm_dmi_ext())
|
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, write_lut(tlm_dmi_ext())
|
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, tgt_adapter(nullptr)
|
||||
#ifdef WITH_SCV
|
||||
, m_db(scv_tr_db::get_default_db())
|
||||
, stream_handle(nullptr)
|
||||
, instr_tr_handle(nullptr)
|
||||
, fetch_tr_handle(nullptr)
|
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#endif
|
||||
{
|
||||
|
||||
initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
|
||||
auto lut_entry = read_lut.getEntry(start);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
|
||||
read_lut.removeEntry(lut_entry);
|
||||
}
|
||||
lut_entry = write_lut.getEntry(start);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
|
||||
write_lut.removeEntry(lut_entry);
|
||||
}
|
||||
});
|
||||
|
||||
SC_THREAD(run);
|
||||
SC_METHOD(clk_cb);
|
||||
sensitive << clk_i;
|
||||
SC_METHOD(rst_cb);
|
||||
sensitive << rst_i;
|
||||
SC_METHOD(sw_irq_cb);
|
||||
sensitive << sw_irq_i;
|
||||
SC_METHOD(timer_irq_cb);
|
||||
sensitive << timer_irq_i;
|
||||
SC_METHOD(global_irq_cb);
|
||||
sensitive << global_irq_i;
|
||||
}
|
||||
|
||||
core_complex::~core_complex() = default;
|
||||
|
||||
void core_complex::trace(sc_trace_file *trf) const {}
|
||||
|
||||
void core_complex::before_end_of_elaboration() {
|
||||
cpu = std::make_unique<core_wrapper>(this);
|
||||
vm = create<arch::rv32imac>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
|
||||
#ifdef WITH_SCV
|
||||
vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
|
||||
#else
|
||||
vm->setDisassEnabled(enable_disass.get_value());
|
||||
#endif
|
||||
auto *srv = debugger::server<debugger::gdb_session>::get();
|
||||
if (srv) tgt_adapter = srv->get_target();
|
||||
if (tgt_adapter)
|
||||
tgt_adapter->add_custom_command(
|
||||
{"sysc", [this](int argc, char *argv[], debugger::out_func of,
|
||||
debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
|
||||
"SystemC sub-commands: break <time>, print_time"});
|
||||
}
|
||||
|
||||
void core_complex::start_of_simulation() {
|
||||
quantum_keeper.reset();
|
||||
if (elf_file.get_value().size() > 0) {
|
||||
istringstream is(elf_file.get_value());
|
||||
string s;
|
||||
while (getline(is, s, ',')) {
|
||||
std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
|
||||
if (reset_address.is_default_value() && start_addr.second == true)
|
||||
reset_address.set_value(start_addr.first);
|
||||
}
|
||||
}
|
||||
#ifdef WITH_SCV
|
||||
if (m_db != nullptr && stream_handle == nullptr) {
|
||||
string basename(this->name());
|
||||
stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
|
||||
instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
|
||||
fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
|
||||
#ifdef WITH_SCV
|
||||
if (m_db == nullptr) return;
|
||||
if (tr_handle.is_active()) tr_handle.end_transaction();
|
||||
tr_handle = instr_tr_handle->begin_transaction();
|
||||
tr_handle.record_attribute("PC", pc);
|
||||
tr_handle.record_attribute("INSTR", instr_str);
|
||||
tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
|
||||
tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value);
|
||||
tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
void core_complex::clk_cb() {
|
||||
curr_clk = clk_i.read();
|
||||
if (curr_clk == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
void core_complex::rst_cb() {
|
||||
if (rst_i.read()) cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
void core_complex::sw_irq_cb() { cpu->local_irq(16, sw_irq_i.read()); }
|
||||
|
||||
void core_complex::timer_irq_cb() { cpu->local_irq(17, timer_irq_i.read()); }
|
||||
|
||||
void core_complex::global_irq_cb() { cpu->local_irq(18, global_irq_i.read()); }
|
||||
|
||||
void core_complex::run() {
|
||||
wait(SC_ZERO_TIME); // separate from elaboration phase
|
||||
do {
|
||||
if (rst_i.read()) {
|
||||
cpu->reset(reset_address.get_value());
|
||||
wait(rst_i.negedge_event());
|
||||
}
|
||||
while (clk_i.read() == SC_ZERO_TIME) {
|
||||
wait(clk_i.value_changed_event());
|
||||
}
|
||||
cpu->set_interrupt_execution(false);
|
||||
vm->start();
|
||||
} while (cpu->get_interrupt_execution());
|
||||
sc_stop();
|
||||
}
|
||||
|
||||
bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
|
||||
auto lut_entry = read_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
return true;
|
||||
} else {
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(data);
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
sc_time delay{quantum_keeper.get_local_time()};
|
||||
#ifdef WITH_SCV
|
||||
if (m_db != nullptr && tr_handle.is_valid()) {
|
||||
if (is_fetch && tr_handle.is_active()) {
|
||||
tr_handle.end_transaction();
|
||||
}
|
||||
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
#endif
|
||||
initiator->b_transport(gp, delay);
|
||||
SCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
return false;
|
||||
}
|
||||
if (gp.is_dmi_allowed()) {
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
tlm_dmi_ext dmi_data;
|
||||
if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
|
||||
if (dmi_data.is_read_allowed())
|
||||
read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
if (dmi_data.is_write_allowed())
|
||||
write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *const data) {
|
||||
auto lut_entry = write_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
return true;
|
||||
} else {
|
||||
write_buf.resize(length);
|
||||
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(write_buf.data());
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
sc_time delay{quantum_keeper.get_local_time()};
|
||||
#ifdef WITH_SCV
|
||||
if (m_db != nullptr && tr_handle.is_valid()) {
|
||||
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
#endif
|
||||
initiator->b_transport(gp, delay);
|
||||
quantum_keeper.set(delay);
|
||||
SCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
return false;
|
||||
}
|
||||
if (gp.is_dmi_allowed()) {
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
tlm_dmi_ext dmi_data;
|
||||
if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
|
||||
if (dmi_data.is_read_allowed())
|
||||
read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
if (dmi_data.is_write_allowed())
|
||||
write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
|
||||
auto lut_entry = read_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
return true;
|
||||
} else {
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(data);
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
return initiator->transport_dbg(gp) == length;
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
|
||||
auto lut_entry = write_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
return true;
|
||||
} else {
|
||||
write_buf.resize(length);
|
||||
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(write_buf.data());
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
return initiator->transport_dbg(gp) == length;
|
||||
}
|
||||
}
|
||||
|
||||
} /* namespace SiFive */
|
||||
} /* namespace sysc */
|
||||
Reference in New Issue
Block a user