moves mmu related code into mmu unit
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56
src/iss/mem/memory_with_htif.h
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56
src/iss/mem/memory_with_htif.h
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@@ -0,0 +1,56 @@
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#ifndef _MEMORY_WITH_HTIF_
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#define _MEMORY_WITH_HTIF_
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#include "iss/arch/riscv_hart_common.h"
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#include "iss/vm_types.h"
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#include <util/logging.h>
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#include <util/sparse_array.h>
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#include "../mem/memory_if.h"
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namespace iss {
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namespace mem {
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template <typename WORD_TYPE> struct memory_with_htif : public memory_elem {
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using this_class = memory_with_htif<WORD_TYPE>;
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constexpr static unsigned WORD_LEN = sizeof(WORD_TYPE) * 8;
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memory_with_htif(arch::priv_if<WORD_TYPE> hart_if)
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: hart_if(hart_if) {}
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~memory_with_htif() = default;
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memory_if get_mem_if() override {
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return memory_if{.rd_mem{util::delegate<rd_mem_func_sig>::from<this_class, &this_class::read_mem>(this)},
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.wr_mem{util::delegate<wr_mem_func_sig>::from<this_class, &this_class::write_mem>(this)}};
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}
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void set_next(memory_if) override {
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// intenrionally left empty, leaf element
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}
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private:
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iss::status read_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t* data) {
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for(auto offs = 0U; offs < length; ++offs) {
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*(data + offs) = mem[(addr + offs) % mem.size()];
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}
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return iss::Ok;
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}
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iss::status write_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t const* data) {
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mem_type::page_type& p = mem(addr / mem.page_size);
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std::copy(data, data + length, p.data() + (addr & mem.page_addr_mask));
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// this->tohost handling in case of riscv-test
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// according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
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if(access && iss::access_type::FUNC && addr == hart_if.tohost) {
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return hart_if.exec_htif(data);
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}
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return iss::Ok;
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}
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protected:
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using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
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mem_type mem;
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arch::priv_if<WORD_TYPE> hart_if;
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};
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} // namespace mem
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} // namespace iss
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#endif // _MEMORY_WITH_HTIF_
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