Initial commit
This commit is contained in:
168
riscv/incl/cli_options.h
Normal file
168
riscv/incl/cli_options.h
Normal file
@ -0,0 +1,168 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CLI_OPTIONS_H_
|
||||
#define _CLI_OPTIONS_H_
|
||||
#include <boost/program_options.hpp>
|
||||
#include <easylogging++.h>
|
||||
|
||||
namespace {
|
||||
const size_t ERROR_IN_COMMAND_LINE = 1;
|
||||
const size_t SUCCESS = 0;
|
||||
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
|
||||
|
||||
|
||||
inline void enable_log_level(el::Configurations& conf, int level){
|
||||
switch(level){
|
||||
case 0:
|
||||
conf.set(el::Level::Fatal, el::ConfigurationType::Enabled, "false");
|
||||
/* no break */
|
||||
case 1:
|
||||
conf.set(el::Level::Error, el::ConfigurationType::Enabled, "false");
|
||||
/* no break */
|
||||
case 2:
|
||||
conf.set(el::Level::Warning, el::ConfigurationType::Enabled, "false");
|
||||
/* no break */
|
||||
case 3:
|
||||
conf.set(el::Level::Info, el::ConfigurationType::Enabled, "false");
|
||||
/* no break */
|
||||
case 4:
|
||||
conf.set(el::Level::Debug, el::ConfigurationType::Enabled, "false");
|
||||
/* no break */
|
||||
case 5:
|
||||
conf.set(el::Level::Trace, el::ConfigurationType::Enabled, "false");
|
||||
/* no break */
|
||||
}
|
||||
}
|
||||
|
||||
inline void configure_default_logger(boost::program_options::variables_map& vm){
|
||||
el::Configurations defaultConf;
|
||||
defaultConf.setToDefault();
|
||||
defaultConf.set(el::Level::Error, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||
defaultConf.set(el::Level::Warning, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||
defaultConf.set(el::Level::Info, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||
defaultConf.set(el::Level::Debug, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||
defaultConf.set(el::Level::Trace, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||
if(vm.count("verbose"))
|
||||
enable_log_level(defaultConf, vm["verbose"].as<int>());
|
||||
if(vm.count("log-file"))
|
||||
defaultConf.set(el::Level::Global,el::ConfigurationType::Filename, vm["log-file"].as<std::string>());
|
||||
// default logger uses default configurations
|
||||
el::Loggers::reconfigureLogger("default", defaultConf);
|
||||
}
|
||||
|
||||
inline void configure_debugger_logger() {
|
||||
// configure the connection logger
|
||||
el::Logger* gdbServerLogger = el::Loggers::getLogger("connection");
|
||||
el::Configurations gdbServerConf;
|
||||
gdbServerConf.setToDefault();
|
||||
gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format,
|
||||
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||
gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format,
|
||||
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||
gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format,
|
||||
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||
gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format,
|
||||
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||
gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format,
|
||||
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||
enable_log_level(gdbServerConf, 5);
|
||||
gdbServerLogger->configure(gdbServerConf);
|
||||
}
|
||||
|
||||
inline void configure_disass_logger(boost::program_options::variables_map& vm) {
|
||||
el::Logger* disassLogger = el::Loggers::getLogger("disass");
|
||||
el::Configurations disassConf;
|
||||
if(vm.count("disass")){
|
||||
auto file_name=vm["disass"].as<std::string>();
|
||||
disassConf.setToDefault();
|
||||
if (file_name.length() > 0) {
|
||||
disassConf.set(el::Level::Global, el::ConfigurationType::ToFile,
|
||||
std::string("true"));
|
||||
disassConf.set(el::Level::Global,
|
||||
el::ConfigurationType::ToStandardOutput, std::string("false"));
|
||||
disassConf.set(el::Level::Global, el::ConfigurationType::Format,
|
||||
std::string("%msg"));
|
||||
disassConf.set(el::Level::Global, el::ConfigurationType::Filename,
|
||||
file_name);
|
||||
std::ofstream str(file_name); // just to clear the file
|
||||
} else {
|
||||
disassConf.set(el::Level::Global, el::ConfigurationType::Format,
|
||||
"%datetime{%H:%m:%s.%g} [%logger] %msg");
|
||||
}
|
||||
} else {
|
||||
enable_log_level(disassConf, 0);
|
||||
}
|
||||
disassLogger->configure(disassConf);
|
||||
}
|
||||
|
||||
} // namespace
|
||||
|
||||
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){
|
||||
namespace po = boost::program_options;
|
||||
po::options_description desc("Options");
|
||||
desc.add_options()
|
||||
("help,h", "Print help message")
|
||||
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
|
||||
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged")
|
||||
("logging-flags", po::value<int>(),"Sets logging flag(s).")
|
||||
("log-file", po::value<std::string>(),"Sets default log file.")
|
||||
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly")
|
||||
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load")
|
||||
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")
|
||||
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
|
||||
("dump-ir", "dump the intermediate representation")
|
||||
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
|
||||
("systemc,s", "Run as SystemC simulation")
|
||||
("time", po::value<int>(), "SystemC siimulation time in ms")
|
||||
("reset,r", po::value<std::string>(), "reset address")
|
||||
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\
|
||||
("mem,m", po::value<std::string>(), "the memory input file");
|
||||
try {
|
||||
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
|
||||
// --help option
|
||||
if ( vm.count("help") ){
|
||||
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
|
||||
return SUCCESS;
|
||||
}
|
||||
po::notify(vm); // throws on error, so do after help in case
|
||||
} catch(po::error& e){
|
||||
// there are problems
|
||||
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
|
||||
std::cerr << desc << std::endl;
|
||||
return ERROR_IN_COMMAND_LINE;
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif /* _CLI_OPTIONS_H_ */
|
200
riscv/incl/iss/arch/minrv_ima.h
Normal file
200
riscv/incl/iss/arch/minrv_ima.h
Normal file
@ -0,0 +1,200 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MINRV_IMA_H_
|
||||
#define _MINRV_IMA_H_
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
#include <iss/vm_if.h>
|
||||
#include <iss/arch/traits.h>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
struct minrv_ima;
|
||||
|
||||
template<>
|
||||
struct traits<minrv_ima> {
|
||||
|
||||
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
|
||||
|
||||
enum reg_e {
|
||||
X0,
|
||||
X1,
|
||||
X2,
|
||||
X3,
|
||||
X4,
|
||||
X5,
|
||||
X6,
|
||||
X7,
|
||||
X8,
|
||||
X9,
|
||||
X10,
|
||||
X11,
|
||||
X12,
|
||||
X13,
|
||||
X14,
|
||||
X15,
|
||||
X16,
|
||||
X17,
|
||||
X18,
|
||||
X19,
|
||||
X20,
|
||||
X21,
|
||||
X22,
|
||||
X23,
|
||||
X24,
|
||||
X25,
|
||||
X26,
|
||||
X27,
|
||||
X28,
|
||||
X29,
|
||||
X30,
|
||||
X31,
|
||||
PC,
|
||||
NUM_REGS,
|
||||
NEXT_PC=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
ICOUNT
|
||||
};
|
||||
|
||||
typedef uint32_t reg_t;
|
||||
|
||||
typedef uint32_t addr_t;
|
||||
|
||||
typedef uint32_t code_word_t; //TODO: check removal
|
||||
|
||||
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
|
||||
|
||||
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
|
||||
|
||||
constexpr static unsigned reg_bit_width(unsigned r) {
|
||||
const uint32_t MinRV_IMA_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
|
||||
return MinRV_IMA_reg_size[r];
|
||||
}
|
||||
|
||||
constexpr static unsigned reg_byte_offset(unsigned r) {
|
||||
const uint32_t MinRV_IMA_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
|
||||
return MinRV_IMA_reg_byte_offset[r];
|
||||
}
|
||||
|
||||
enum sreg_flag_e {FLAGS};
|
||||
|
||||
enum mem_type_e {MEM,CSR,FENCE,RES};
|
||||
|
||||
};
|
||||
|
||||
struct minrv_ima: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<minrv_ima>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<minrv_ima>::phys_addr_t;
|
||||
using reg_t = typename traits<minrv_ima>::reg_t;
|
||||
using addr_t = typename traits<minrv_ima>::addr_t;
|
||||
|
||||
minrv_ima();
|
||||
~minrv_ima();
|
||||
|
||||
void reset(uint64_t address=0);
|
||||
|
||||
// virtual void loadFile(std::string name, int type=-1);
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
|
||||
void get_reg(short idx, std::vector<uint8_t>& value) override;
|
||||
void set_reg(short idx, const std::vector<uint8_t>& value) override;
|
||||
|
||||
bool get_flag(int flag) override;
|
||||
void set_flag(int, bool value) override;
|
||||
|
||||
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override;
|
||||
|
||||
void notify_phase(exec_phase phase){
|
||||
if(phase==ISTART){
|
||||
++reg.icount;
|
||||
reg.PC=reg.NEXT_PC;
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t get_icount() { return reg.icount;}
|
||||
|
||||
virtual phys_addr_t v2p(const iss::addr_t& pc);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
|
||||
|
||||
protected:
|
||||
struct MinRV_IMA_regs {
|
||||
uint32_t X0;
|
||||
uint32_t X1;
|
||||
uint32_t X2;
|
||||
uint32_t X3;
|
||||
uint32_t X4;
|
||||
uint32_t X5;
|
||||
uint32_t X6;
|
||||
uint32_t X7;
|
||||
uint32_t X8;
|
||||
uint32_t X9;
|
||||
uint32_t X10;
|
||||
uint32_t X11;
|
||||
uint32_t X12;
|
||||
uint32_t X13;
|
||||
uint32_t X14;
|
||||
uint32_t X15;
|
||||
uint32_t X16;
|
||||
uint32_t X17;
|
||||
uint32_t X18;
|
||||
uint32_t X19;
|
||||
uint32_t X20;
|
||||
uint32_t X21;
|
||||
uint32_t X22;
|
||||
uint32_t X23;
|
||||
uint32_t X24;
|
||||
uint32_t X25;
|
||||
uint32_t X26;
|
||||
uint32_t X27;
|
||||
uint32_t X28;
|
||||
uint32_t X29;
|
||||
uint32_t X30;
|
||||
uint32_t X31;
|
||||
uint32_t PC;
|
||||
uint32_t NEXT_PC;
|
||||
uint32_t trap_state, pending_trap, machine_state;
|
||||
uint64_t icount;
|
||||
} reg;
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _MINRV_IMA_H_ */
|
1249
riscv/incl/iss/arch/riscv_core.h
Normal file
1249
riscv/incl/iss/arch/riscv_core.h
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user