remove clutter from core descriptions, added instr alignment setting

gen_input/CoreDSL-Instruction-Set-Description

@@ -1 +1 @@
-Subproject commit 8d9a0fb1493b762014c330c71ac8cef96753d302
+Subproject commit 89dabd00e3380d41070b126f8d6d1548056619c1

gen_input/TGC_B.core_desc

@@ -4,13 +4,10 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
 Core TGC_B provides RV32I {
 	architectural_state {
-        unsigned XLEN=32;
+        XLEN=32;
-        unsigned PCLEN=32;
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000000000100000000;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
 	}
 }
 

gen_input/TGC_C.core_desc

@@ -4,12 +4,9 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
 Core TGC_C provides RV32I, RV32M, RV32IC {
     architectural_state {
-        unsigned XLEN=32;
+        XLEN=32;
-        unsigned PCLEN=32;
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
     }
 }

gen_input/TGC_D.core_desc

@@ -4,8 +4,7 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
 Core TGC_D provides RV32I, RV32M, RV32IC {
     architectural_state {
-        unsigned XLEN=32;
+        XLEN=32;
-        unsigned PCLEN=32;
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000001000100000100;

gen_input/TGC_D_XRB_MAC.core_desc

@@ -64,8 +64,7 @@ InstructionSet X_RB_MAC extends RISCVBase {
 
 Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
     architectural_state {
-        unsigned XLEN=32;
+        XLEN=32;
-        unsigned PCLEN=32;
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000001000100000100;

incl/iss/arch/tgc_c.h

@@ -51,9 +51,9 @@ template <> struct traits<tgc_c> {
         {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
  
     static constexpr std::array<const char*, 35> reg_aliases{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV"}};
 
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
+    enum constants {MISA_VAL=0b01000000000000000001000100000100, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 

src/vm/interp/vm_tgc_c.cpp

@@ -467,8 +467,13 @@ private:
         // execute instruction
         try {
         {
-            if(rd != 0) *(X+rd) = *PC + 4; 
+            if(imm % traits::INSTR_ALIGNMENT) {
-            pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
+                raise(0,  0);
+            }
+            else {
+                if(rd != 0) *(X+rd) = *PC + 4; 
+                pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
+            }
         }
         } catch(...){}
         // post execution stuff
@@ -513,8 +518,13 @@ private:
         try {
         {
             int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm);
-            if(rd != 0) *(X+rd) = *PC + 4; 
+            if(new_pc % traits::INSTR_ALIGNMENT) {
-            pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
+                raise(0,  0);
+            }
+            else {
+                if(rd != 0) *(X+rd) = *PC + 4; 
+                pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
+            }
         }
         } catch(...){}
         // post execution stuff
@@ -557,7 +567,12 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        {
+            if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+                raise(0,  0);
+            }
+            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+        }
         } catch(...){}
         // post execution stuff
         if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0,  0);
@@ -599,7 +614,12 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        {
+            if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+                raise(0,  0);
+            }
+            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+        }
         } catch(...){}
         // post execution stuff
         if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0,  0);
@@ -641,7 +661,12 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        {
+            if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+                raise(0,  0);
+            }
+            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+        }
         } catch(...){}
         // post execution stuff
         if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0,  0);
@@ -683,7 +708,12 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        {
+            if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+                raise(0,  0);
+            }
+            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+        }
         } catch(...){}
         // post execution stuff
         if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0,  0);
@@ -725,7 +755,12 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        {
+            if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+                raise(0,  0);
+            }
+            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+        }
         } catch(...){}
         // post execution stuff
         if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0,  0);
@@ -767,7 +802,12 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        {
+            if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+                raise(0,  0);
+            }
+            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+        }
         } catch(...){}
         // post execution stuff
         if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0,  0);