fixes sc_core_adapter wrt refactored memory hierarchy
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@ -419,7 +419,7 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t
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gp.set_extension(preExt);
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}
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auto pre_delay = delay;
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dbus->b_transport(gp, delay);
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sckt->b_transport(gp, delay);
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if(pre_delay > delay) {
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quantum_keeper.reset();
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} else {
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@ -14,15 +14,21 @@
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#include <iss/vm_types.h>
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#include <scc/report.h>
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#include <util/ities.h>
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#include <iss/mem/memory_if.h>
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namespace sysc {
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template <typename PLAT> class sc_core_adapter : public PLAT, public sc_core_adapter_if {
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public:
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using this_class = sc_core_adapter<PLAT>;
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using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
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using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
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using heart_state_t = typename PLAT::hart_state_type;
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sc_core_adapter(sysc::tgfs::core_complex_if* owner)
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: owner(owner) {}
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: owner(owner) {
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this->csr_rd_cb[iss::arch::time] = MK_CSR_RD_CB(read_time);
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if(sizeof(reg_t) == 4)
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this->csr_rd_cb[iss::arch::timeh] = MK_CSR_RD_CB(read_time);
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this->memories.replace_last(*this);
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}
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iss::arch_if* get_arch_if() override { return this; }
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@ -60,18 +66,24 @@ public:
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}
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};
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iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t* const data) override {
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if(addr.access && iss::access_type::DEBUG)
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return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
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iss::mem::memory_if get_mem_if() override {
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return iss::mem::memory_if{
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.rd_mem{util::delegate<iss::mem::rd_mem_func_sig>::from<this_class, &this_class::read_mem>(this)},
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.wr_mem{util::delegate<iss::mem::wr_mem_func_sig>::from<this_class, &this_class::write_mem>(this)}};
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}
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iss::status read_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t* data) {
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if(access && iss::access_type::DEBUG)
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return owner->read_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
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else {
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return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
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return owner->read_mem(addr, length, data, is_fetch(access)) ? iss::Ok : iss::Err;
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}
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}
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iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data) override {
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if(addr.access && iss::access_type::DEBUG)
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return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
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if(addr.val == this->tohost) {
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iss::status write_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t const* data) {
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if(access && iss::access_type::DEBUG)
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return owner->write_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
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if(addr == this->tohost) {
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reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
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// Extract Device (bits 63:56)
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uint8_t device = sizeof(reg_t) == 4 ? 0 : (cur_data >> 56) & 0xFF;
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@ -117,31 +129,20 @@ public:
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this->interrupt_sim = payload_addr;
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return iss::Ok;
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}
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auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
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// clear MTIP on mtimecmp write
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if(addr.val == 0x2004000) {
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reg_t val;
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this->read_csr(iss::arch::mip, val);
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if(val & (1ULL << 7))
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this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
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}
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auto res = owner->write_mem(addr, length, data) ? iss::Ok : iss::Err;
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return res;
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}
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iss::status read_csr(unsigned addr, reg_t& val) override {
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if((addr == iss::arch::time || addr == iss::arch::timeh)) {
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uint64_t time_val = owner->mtime_i.get_interface() ? owner->mtime_i.read() : 0;
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if(addr == iss::arch::time) {
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val = static_cast<reg_t>(time_val);
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} else if(addr == iss::arch::timeh) {
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if(sizeof(reg_t) != 4)
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return iss::Err;
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val = static_cast<reg_t>(time_val >> 32);
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}
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return iss::Ok;
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} else {
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return PLAT::read_csr(addr, val);
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iss::status read_time(unsigned addr, reg_t& val) {
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uint64_t time_val = owner->mtime_i.get_interface() ? owner->mtime_i.read() : 0;
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if(addr == iss::arch::time) {
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val = static_cast<reg_t>(time_val);
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} else if(addr == iss::arch::timeh) {
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if(sizeof(reg_t) != 4)
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return iss::Err;
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val = static_cast<reg_t>(time_val >> 32);
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}
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return iss::Ok;
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}
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void wait_until(uint64_t flags) override {
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