Added cycle estimator and remove deprecated functions
This commit is contained in:
parent
a690981957
commit
38471b8193
2
dbt-core
2
dbt-core
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@ -1 +1 @@
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Subproject commit 11ec5cecc1e07b1401830c06d86fe88e3c246b46
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Subproject commit 2d372f9eb694f14b98f10c75e93a9b33d9d17a5d
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@ -108,12 +108,13 @@ public:
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~core_complex();
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inline void sync() {
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quantum_keeper.inc(curr_clk);
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inline void sync(uint64_t cycle) {
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quantum_keeper.inc(curr_clk*(cycle-last_sync_cycle));
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if (quantum_keeper.need_sync()) {
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wait(quantum_keeper.get_local_time());
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quantum_keeper.reset();
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}
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last_sync_cycle=cycle;
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}
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bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
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@ -135,6 +136,7 @@ protected:
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void sw_irq_cb();
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void timer_irq_cb();
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void global_irq_cb();
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uint64_t last_sync_cycle = 0;
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util::range_lut<tlm_dmi_ext> read_lut, write_lut;
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tlm_utils::tlm_quantumkeeper quantum_keeper;
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std::vector<uint8_t> write_buf;
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@ -200,7 +200,7 @@ int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func
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void core_wrapper::notify_phase(exec_phase p) {
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if(p == ISTART)
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owner->sync();
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owner->sync(this->reg.icount+cycle_offset);
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}
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core_complex::core_complex(sc_core::sc_module_name name)
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@ -35,12 +35,13 @@
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#ifndef _RISCV_CORE_H_
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#define _RISCV_CORE_H_
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#include "iss/arch/traits.h"
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#include "iss/arch_if.h"
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#include "iss/log_categories.h"
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#include "iss/vm_if.h"
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#include "iss/instrumentation_if.h"
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#include <elfio/elfio.hpp>
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#include <iomanip>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/log_categories.h>
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#include <iss/vm_if.h>
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#include <sstream>
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#include <unordered_map>
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#include <util/ities.h>
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@ -463,6 +464,7 @@ public:
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virtual uint64_t leave_trap(uint64_t flags) override;
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void wait_until(uint64_t flags) override;
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void disass_output(uint64_t pc, const std::string instr) override {
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std::stringstream s;
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s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
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@ -470,26 +472,54 @@ public:
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CLOG(INFO, disass) << "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<instr<<"\t"<<s.str();
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};
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iss::instrumentation_if* get_instrumentation_if() override {return &instr_if;}
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protected:
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struct riscv_instrumentation_if : public iss::instrumentation_if{
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riscv_instrumentation_if(riscv_hart_msu_vp<BASE>& arch):arch(arch){}
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/**
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* get the name of this architecture
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*
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* @return the name of this architecture
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*/
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const std::string core_type_name() const override {return traits<BASE>::core_type;}
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virtual uint64_t get_pc(){ return arch.get_pc(); };
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virtual uint64_t get_next_pc(){ return arch.get_next_pc(); };
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virtual void set_curr_instr_cycles(unsigned cycles){ arch.cycle_offset+=cycles-1; };
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riscv_hart_msu_vp<BASE>& arch;
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};
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friend struct riscv_instrumentation_if;
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addr_t get_pc(){return this->reg.PC;}
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addr_t get_next_pc(){return this->reg.NEXT_PC;}
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virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
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virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
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virtual iss::status read_csr(unsigned addr, reg_t &val);
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virtual iss::status write_csr(unsigned addr, reg_t val);
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hart_state<reg_t> state;
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uint64_t cycle_offset;
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reg_t fault_data;
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std::array<vm_info,2> vm;
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uint64_t tohost = tohost_dflt;
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uint64_t fromhost = fromhost_dflt;
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unsigned to_host_wr_cnt = 0;
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riscv_instrumentation_if instr_if;
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reg_t fault_data;
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using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
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using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
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using csr_page_type = typename csr_type::page_type;
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mem_type mem;
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csr_type csr;
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hart_state<reg_t> state;
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std::array<vm_info,2> vm;
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void update_vm_info();
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unsigned to_host_wr_cnt = 0;
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std::stringstream uart_buf;
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std::unordered_map<reg_t, uint64_t> ptw;
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std::unordered_map<uint64_t, uint8_t> atomic_reservation;
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@ -513,7 +543,7 @@ protected:
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template <typename BASE>
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riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
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: state() {
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: state(), cycle_offset(0), instr_if(*this) {
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csr[misa] = hart_state<reg_t>::get_misa();
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uart_buf.str("");
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// read-only registers
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@ -814,7 +844,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
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auto cycle_val=this->cycles ? this->cycles : this->reg.icount;
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auto cycle_val= this->reg.icount + cycle_offset;
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if (addr == mcycle) {
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val = static_cast<reg_t>(cycle_val);
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} else if (addr == mcycleh) {
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@ -825,7 +855,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigne
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
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uint64_t time_val=(this->cycles?this->cycles:this->reg.icount) / (100000000/32768-1); //-> ~3052;
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uint64_t time_val=(this->reg.icount + cycle_offset) / (100000000/32768-1); //-> ~3052;
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if (addr == time) {
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val = static_cast<reg_t>(time_val);
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} else if (addr == timeh) {
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@ -130,8 +130,6 @@ struct rv32imac: public arch_if {
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rv32imac();
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~rv32imac();
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const std::string core_type_name() const override {return traits<rv32imac>::core_type;}
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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@ -201,8 +199,6 @@ protected:
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std::array<address_type, 4> addr_mode;
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uint64_t cycles = 0;
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};
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}
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@ -130,8 +130,6 @@ struct rv64ia: public arch_if {
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rv64ia();
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~rv64ia();
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const std::string core_type_name() const override {return traits<rv64ia>::core_type;}
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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@ -201,8 +199,6 @@ protected:
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std::array<address_type, 4> addr_mode;
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uint64_t cycles = 0;
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};
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}
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@ -205,7 +205,7 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
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// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
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// arch::traits<ARCH>::reg_e>(reg_no))/8;
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auto *reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)) / 8;
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auto reg_width = arch::traits<ARCH>::reg_bit_width(reg_no) / 8;
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data.resize(reg_width);
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avail.resize(reg_width);
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auto offset = traits<ARCH>::reg_byte_offset(reg_no);
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@ -319,12 +319,14 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int typ
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template <typename ARCH> status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
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std::function<void(unsigned)> stop_callback) {
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unsigned reg_no = arch::traits<ARCH>::PC;
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std::vector<uint8_t> data(8);
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*(reinterpret_cast<uint64_t *>(&data[0])) = addr;
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core->set_reg(reg_no, data);
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auto* reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_width(arch::traits<ARCH>::PC) / 8;
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auto offset = traits<ARCH>::reg_byte_offset(arch::traits<ARCH>::PC);
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const uint8_t* iter = reinterpret_cast<const uint8_t*>(&addr);
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std::copy(iter, iter + reg_width, reg_base);
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return resume_from_current(step, sig, thread, stop_callback);
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
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const std::string res{
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"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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@ -0,0 +1,96 @@
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/*******************************************************************************
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* Copyright (C) 2017, MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contributors:
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* eyck@minres.com - initial API and implementation
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******************************************************************************/
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#ifndef _ISS_PLUGIN_CYCLE_ESTIMATE_H_
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#define _ISS_PLUGIN_CYCLE_ESTIMATE_H_
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#include "iss/vm_plugin.h"
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#include "iss/instrumentation_if.h"
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#include <json/json.h>
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#include <string>
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#include <unordered_map>
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namespace iss {
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namespace plugin {
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class cycle_estimate: public iss::vm_plugin {
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BEGIN_BF_DECL(instr_desc, uint32_t)
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BF_FIELD(taken, 24, 8)
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BF_FIELD(not_taken, 16, 8)
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BF_FIELD(size, 0, 16)
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instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
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this->size=size;
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this->taken=taken;
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this->not_taken=not_taken;
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}
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END_BF_DECL();
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public:
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cycle_estimate() = delete;
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cycle_estimate(const cycle_estimate& ) = delete;
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cycle_estimate(const cycle_estimate&&) = delete;
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cycle_estimate(std::string config_file_name);
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virtual ~cycle_estimate();
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cycle_estimate& operator=(const cycle_estimate& ) = delete;
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cycle_estimate& operator=(const cycle_estimate&& ) = delete;
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bool registration(const char* const version, vm_if& arch) override;
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sync_type get_sync() override {return POST_SYNC;};
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void callback(instr_info_t instr_info) override;
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private:
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iss::instrumentation_if* arch_instr;
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std::vector<instr_desc> delays;
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struct pair_hash {
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size_t operator()(const std::pair<uint64_t, uint64_t>& p) const{
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std::hash<uint64_t> hash;
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return hash(p.first)+hash(p.second);
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}
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};
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std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
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Json::Value root;
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};
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}
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}
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#endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */
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@ -32,8 +32,8 @@
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* eyck@minres.com - initial API and implementation
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******************************************************************************/
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#ifndef _ISS_PLUGIN_CYCLE_COUNTER_H_
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#define _ISS_PLUGIN_CYCLE_COUNTER_H_
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#ifndef _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
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#define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
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#include <iss/vm_plugin.h>
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#include <json/json.h>
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@ -52,15 +52,23 @@ class instruction_count: public iss::vm_plugin {
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public:
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instruction_count() = delete;
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instruction_count(const instruction_count& ) = delete;
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instruction_count(const instruction_count&&) = delete;
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instruction_count(std::string config_file_name);
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virtual ~instruction_count();
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instruction_count& operator=(const instruction_count& ) = delete;
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instruction_count& operator=(const instruction_count&& ) = delete;
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bool registration(const char* const version, vm_if& arch) override;
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sync_type get_sync() override {return POST_SYNC;};
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void callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) override;
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void callback(instr_info_t instr_info) override;
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private:
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Json::Value root;
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std::vector<instr_delay> delays;
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@ -70,4 +78,4 @@ private:
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}
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}
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#endif /* _ISS_PLUGIN_CYCLE_COUNTER_H_ */
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#endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */
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@ -7,6 +7,7 @@ set(LIB_SOURCES
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internal/vm_rv32imac.cpp
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internal/vm_rv64ia.cpp
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plugin/instruction_count.cpp
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plugin/cycle_estimate.cpp
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)
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set(APP_HEADERS )
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@ -43,6 +43,7 @@
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#include <iss/jit/MCJIThelper.h>
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#include <iss/log_categories.h>
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#include <iss/plugin/instruction_count.h>
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#include <iss/plugin/cycle_estimate.h>
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namespace po = boost::program_options;
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@ -102,24 +103,19 @@ int main(int argc, char *argv[]) {
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// instantiate the simulator
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std::unique_ptr<iss::vm_if> vm{nullptr};
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std::string isa_opt(clim["isa"].as<std::string>());
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iss::plugin::instruction_count cc_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
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iss::plugin::instruction_count ic_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
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iss::plugin::cycle_estimate ce_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
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if (isa_opt.substr(0, 4)=="rv64") {
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iss::arch::rv64ia* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
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vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
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} else if (isa_opt.substr(0, 4)=="rv32") {
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iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
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vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
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// vm->register_plugin(cc_plugin);
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//vm->register_plugin(ce_plugin);
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} else {
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LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
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return 127;
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}
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if (clim.count("elf"))
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for (std::string input : clim["elf"].as<std::vector<std::string>>())
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vm->get_arch()->load_file(input);
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if (clim.count("mem"))
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vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
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for (std::string input : args) vm->get_arch()->load_file(input);// treat remaining arguments as elf files
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if (clim.count("disass")) {
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vm->setDisassEnabled(true);
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LOGGER(disass)::reporting_level() = logging::INFO;
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@ -130,19 +126,29 @@ int main(int argc, char *argv[]) {
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LOGGER(disass)::print_severity() = false;
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}
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}
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uint64_t start_address=0;
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if (clim.count("mem"))
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vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
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if (clim.count("elf"))
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for (std::string input : clim["elf"].as<std::vector<std::string>>()){
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auto start_addr = vm->get_arch()->load_file(input);
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if(start_addr.second)
|
||||
start_address=start_addr.first;
|
||||
}
|
||||
for (std::string input : args){
|
||||
auto start_addr = vm->get_arch()->load_file(input);// treat remaining arguments as elf files
|
||||
if(start_addr.second)
|
||||
start_address=start_addr.first;
|
||||
}
|
||||
if (clim.count("reset")) {
|
||||
auto str = clim["reset"].as<std::string>();
|
||||
auto start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), 0, 16) : std::stoull(str, 0, 10);
|
||||
vm->reset(start_address);
|
||||
} else {
|
||||
vm->reset();
|
||||
start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), 0, 16) : std::stoull(str, 0, 10);
|
||||
}
|
||||
int64_t cycles = -1;
|
||||
cycles = clim["instructions"].as<int64_t>();
|
||||
vm->reset(start_address);
|
||||
auto cycles = clim["instructions"].as<int64_t>();
|
||||
return vm->start(cycles, dump);
|
||||
} catch (std::exception &e) {
|
||||
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
|
||||
<< std::endl;
|
||||
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
|
||||
return 2;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -0,0 +1,89 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2017, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#include "iss/plugin/cycle_estimate.h"
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
#include <util/logging.h>
|
||||
#include <fstream>
|
||||
|
||||
iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
|
||||
: arch_instr(nullptr)
|
||||
{
|
||||
if (config_file_name.length() > 0) {
|
||||
std::ifstream is(config_file_name);
|
||||
if (is.is_open()) {
|
||||
try {
|
||||
is >> root;
|
||||
} catch (Json::RuntimeError &e) {
|
||||
LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
}
|
||||
} else {
|
||||
LOG(ERROR) << "Could not open input file " << config_file_name;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
iss::plugin::cycle_estimate::~cycle_estimate() {
|
||||
}
|
||||
|
||||
bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
|
||||
arch_instr = vm.get_arch()->get_instrumentation_if();
|
||||
const std::string core_name = arch_instr->core_type_name();
|
||||
Json::Value &val = root[core_name];
|
||||
if(val.isArray()){
|
||||
delays.reserve(val.size());
|
||||
for(auto it:val){
|
||||
auto name = it["name"];
|
||||
auto size = it["size"];
|
||||
auto delay = it["delay"];
|
||||
if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
|
||||
if(delay.isUInt()){
|
||||
delays.push_back(instr_desc{size.asUInt(), delay.asUInt(), 0});
|
||||
} else {
|
||||
delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
|
||||
}
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
|
||||
auto entry = delays[instr_info.instr_id];
|
||||
bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
|
||||
if(taken && entry.taken > 1 ) // 1 is the default increment per instruction
|
||||
arch_instr->set_curr_instr_cycles(entry.taken);
|
||||
if(!taken && entry.not_taken > 1) // 1 is the default increment per instruction
|
||||
arch_instr->set_curr_instr_cycles(entry.not_taken);
|
||||
}
|
|
@ -32,7 +32,8 @@
|
|||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#include "../../incl/iss/plugin/instruction_count.h"
|
||||
#include "iss/plugin/instruction_count.h"
|
||||
#include "iss/instrumentation_if.h"
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
#include <util/logging.h>
|
||||
|
@ -63,7 +64,7 @@ iss::plugin::instruction_count::~instruction_count() {
|
|||
}
|
||||
|
||||
bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
|
||||
const std::string core_name = vm.get_arch()->core_type_name();
|
||||
const std::string core_name = vm.get_arch()->get_instrumentation_if()->core_type_name();
|
||||
Json::Value &val = root[core_name];
|
||||
if(val.isArray()){
|
||||
delays.reserve(val.size());
|
||||
|
@ -85,6 +86,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
|
|||
return true;
|
||||
}
|
||||
|
||||
void iss::plugin::instruction_count::callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) {
|
||||
rep_counts[instr_id]++;
|
||||
void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
|
||||
rep_counts[instr_info.instr_id]++;
|
||||
}
|
||||
|
|
|
@ -1 +1 @@
|
|||
Subproject commit 9d993c15a45b442aaad5a20c9b087c21ceac5b07
|
||||
Subproject commit ac8bd1d2912996c0ec526963f6f6bb862555402f
|
Loading…
Reference in New Issue