Added cycle estimator and remove deprecated functions

dbt-core

@@ -1 +1 @@
-Subproject commit 11ec5cecc1e07b1401830c06d86fe88e3c246b46
+Subproject commit 2d372f9eb694f14b98f10c75e93a9b33d9d17a5d

riscv.sc/incl/sysc/SiFive/core_complex.h

@@ -108,12 +108,13 @@ public:
 
     ~core_complex();
 
-    inline void sync() {
+    inline void sync(uint64_t cycle) {
-        quantum_keeper.inc(curr_clk);
+        quantum_keeper.inc(curr_clk*(cycle-last_sync_cycle));
         if (quantum_keeper.need_sync()) {
             wait(quantum_keeper.get_local_time());
             quantum_keeper.reset();
         }
+        last_sync_cycle=cycle;
     }
 
     bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
@@ -135,6 +136,7 @@ protected:
     void sw_irq_cb();
     void timer_irq_cb();
     void global_irq_cb();
+    uint64_t last_sync_cycle = 0;
     util::range_lut<tlm_dmi_ext> read_lut, write_lut;
     tlm_utils::tlm_quantumkeeper quantum_keeper;
     std::vector<uint8_t> write_buf;

riscv.sc/src/sysc/core_complex.cpp

@@ -200,7 +200,7 @@ int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func
 
 void core_wrapper::notify_phase(exec_phase p) {
     if(p == ISTART)
-        owner->sync();
+        owner->sync(this->reg.icount+cycle_offset);
 }
 
 core_complex::core_complex(sc_core::sc_module_name name)

riscv/incl/iss/arch/riscv_hart_msu_vp.h

@@ -35,12 +35,13 @@
 #ifndef _RISCV_CORE_H_
 #define _RISCV_CORE_H_
 
+#include "iss/arch/traits.h"
+#include "iss/arch_if.h"
+#include "iss/log_categories.h"
+#include "iss/vm_if.h"
+#include "iss/instrumentation_if.h"
 #include <elfio/elfio.hpp>
 #include <iomanip>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/log_categories.h>
-#include <iss/vm_if.h>
 #include <sstream>
 #include <unordered_map>
 #include <util/ities.h>
@@ -463,6 +464,7 @@ public:
     virtual uint64_t leave_trap(uint64_t flags) override;
     void wait_until(uint64_t flags) override;
 
+
     void disass_output(uint64_t pc, const std::string instr) override {
         std::stringstream s;
         s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
@@ -470,26 +472,54 @@ public:
         CLOG(INFO, disass) << "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<instr<<"\t"<<s.str();
     };
 
+    iss::instrumentation_if* get_instrumentation_if() override {return &instr_if;}
+
 protected:
+    struct riscv_instrumentation_if : public iss::instrumentation_if{
+
+    	riscv_instrumentation_if(riscv_hart_msu_vp<BASE>& arch):arch(arch){}
+        /**
+         * get the name of this architecture
+         *
+         * @return the name of this architecture
+         */
+    	const std::string core_type_name() const override {return traits<BASE>::core_type;}
+
+        virtual uint64_t get_pc(){ return arch.get_pc(); };
+
+    	virtual uint64_t get_next_pc(){ return arch.get_next_pc(); };
+
+    	virtual void set_curr_instr_cycles(unsigned cycles){ arch.cycle_offset+=cycles-1; };
+
+    	riscv_hart_msu_vp<BASE>& arch;
+    };
+
+    friend struct riscv_instrumentation_if;
+    addr_t get_pc(){return this->reg.PC;}
+    addr_t get_next_pc(){return this->reg.NEXT_PC;}
+
+
     virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
     virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
 
     virtual iss::status read_csr(unsigned addr, reg_t &val);
     virtual iss::status write_csr(unsigned addr, reg_t val);
 
+    hart_state<reg_t> state;
+    uint64_t cycle_offset;
+    reg_t fault_data;
+    std::array<vm_info,2> vm;
     uint64_t tohost = tohost_dflt;
     uint64_t fromhost = fromhost_dflt;
+    unsigned to_host_wr_cnt = 0;
+    riscv_instrumentation_if instr_if;
 
-    reg_t fault_data;
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
     using csr_page_type = typename csr_type::page_type;
     mem_type mem;
     csr_type csr;
-    hart_state<reg_t> state;
-    std::array<vm_info,2> vm;
     void update_vm_info();
-    unsigned to_host_wr_cnt = 0;
     std::stringstream uart_buf;
     std::unordered_map<reg_t, uint64_t> ptw;
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
@@ -513,7 +543,7 @@ protected:
 
 template <typename BASE>
 riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
-: state() {
+: state(), cycle_offset(0), instr_if(*this) {
     csr[misa] = hart_state<reg_t>::get_misa();
     uart_buf.str("");
     // read-only registers
@@ -814,7 +844,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val=this->cycles ? this->cycles : this->reg.icount;
+    auto cycle_val= this->reg.icount + cycle_offset;
     if (addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
@@ -825,7 +855,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigne
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
-	uint64_t time_val=(this->cycles?this->cycles:this->reg.icount) / (100000000/32768-1); //-> ~3052;
+	uint64_t time_val=(this->reg.icount + cycle_offset) / (100000000/32768-1); //-> ~3052;
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {

riscv/incl/iss/arch/rv32imac.h

@@ -130,8 +130,6 @@ struct rv32imac: public arch_if {
     rv32imac();
     ~rv32imac();
 
-	const std::string core_type_name() const override {return traits<rv32imac>::core_type;}
-	
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
@@ -201,8 +199,6 @@ protected:
 
     std::array<address_type, 4> addr_mode;
 
-    uint64_t cycles = 0;
-
 };
 
 }

riscv/incl/iss/arch/rv64ia.h

@@ -130,8 +130,6 @@ struct rv64ia: public arch_if {
     rv64ia();
     ~rv64ia();
 
-	const std::string core_type_name() const override {return traits<rv64ia>::core_type;}
-	
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
@@ -201,8 +199,6 @@ protected:
 
     std::array<address_type, 4> addr_mode;
 
-    uint64_t cycles = 0;
-
 };
 
 }

riscv/incl/iss/debugger/riscv_target_adapter.h

@@ -205,7 +205,7 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
         auto *reg_base = core->get_regs_base_ptr();
-        auto reg_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)) / 8;
+        auto reg_width = arch::traits<ARCH>::reg_bit_width(reg_no) / 8;
         data.resize(reg_width);
         avail.resize(reg_width);
         auto offset = traits<ARCH>::reg_byte_offset(reg_no);
@@ -319,12 +319,14 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int typ
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
         std::function<void(unsigned)> stop_callback) {
-    unsigned reg_no = arch::traits<ARCH>::PC;
+    auto* reg_base = core->get_regs_base_ptr();
-    std::vector<uint8_t> data(8);
+    auto reg_width = arch::traits<ARCH>::reg_bit_width(arch::traits<ARCH>::PC) / 8;
-    *(reinterpret_cast<uint64_t *>(&data[0])) = addr;
+    auto offset = traits<ARCH>::reg_byte_offset(arch::traits<ARCH>::PC);
-    core->set_reg(reg_no, data);
+    const uint8_t* iter = reinterpret_cast<const uint8_t*>(&addr);
+    std::copy(iter, iter + reg_width, reg_base);
     return resume_from_current(step, sig, thread, stop_callback);
 }
+
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
     const std::string res{
         "<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"

riscv/incl/iss/plugin/cycle_estimate.h

@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Copyright (C) 2017, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#ifndef _ISS_PLUGIN_CYCLE_ESTIMATE_H_
+#define _ISS_PLUGIN_CYCLE_ESTIMATE_H_
+
+#include "iss/vm_plugin.h"
+#include "iss/instrumentation_if.h"
+#include <json/json.h>
+#include <string>
+#include <unordered_map>
+
+namespace iss {
+
+namespace plugin {
+
+class cycle_estimate: public iss::vm_plugin {
+	BEGIN_BF_DECL(instr_desc, uint32_t)
+		BF_FIELD(taken, 24, 8)
+		BF_FIELD(not_taken, 16, 8)
+		BF_FIELD(size, 0, 16)
+		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
+			this->size=size;
+			this->taken=taken;
+			this->not_taken=not_taken;
+		}
+	END_BF_DECL();
+
+public:
+	cycle_estimate() = delete;
+
+	cycle_estimate(const cycle_estimate& ) = delete;
+
+	cycle_estimate(const cycle_estimate&&) = delete;
+
+	cycle_estimate(std::string config_file_name);
+
+	virtual ~cycle_estimate();
+
+	cycle_estimate& operator=(const cycle_estimate& ) = delete;
+
+	cycle_estimate& operator=(const cycle_estimate&& ) = delete;
+
+	bool registration(const char* const version, vm_if& arch) override;
+
+	sync_type get_sync() override {return POST_SYNC;};
+
+	void callback(instr_info_t instr_info) override;
+private:
+    iss::instrumentation_if* arch_instr;
+    std::vector<instr_desc> delays;
+    struct pair_hash {
+    	size_t operator()(const std::pair<uint64_t, uint64_t>& p) const{
+    		std::hash<uint64_t> hash;
+    		return hash(p.first)+hash(p.second);
+    	}
+    };
+    std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
+    Json::Value root;
+};
+
+}
+}
+
+#endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */

riscv/incl/iss/plugin/instruction_count.h

@@ -32,8 +32,8 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#ifndef _ISS_PLUGIN_CYCLE_COUNTER_H_
+#ifndef _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
-#define _ISS_PLUGIN_CYCLE_COUNTER_H_
+#define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
 
 #include <iss/vm_plugin.h>
 #include <json/json.h>
@@ -52,15 +52,23 @@ class instruction_count: public iss::vm_plugin {
 public:
 	instruction_count() = delete;
 
+	instruction_count(const instruction_count& ) = delete;
+
+	instruction_count(const instruction_count&&) = delete;
+
 	instruction_count(std::string config_file_name);
 
 	virtual ~instruction_count();
 
+	instruction_count& operator=(const instruction_count& ) = delete;
+
+	instruction_count& operator=(const instruction_count&& ) = delete;
+
 	bool registration(const char* const version, vm_if& arch) override;
 
 	sync_type get_sync() override {return POST_SYNC;};
 
-	void callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) override;
+	void callback(instr_info_t instr_info) override;
 private:
     Json::Value root;
     std::vector<instr_delay> delays;
@@ -70,4 +78,4 @@ private:
 }
 }
 
-#endif /* _ISS_PLUGIN_CYCLE_COUNTER_H_ */
+#endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */

riscv/src/CMakeLists.txt

@@ -7,6 +7,7 @@ set(LIB_SOURCES
     internal/vm_rv32imac.cpp
     internal/vm_rv64ia.cpp
     plugin/instruction_count.cpp
+    plugin/cycle_estimate.cpp
 )
 
 set(APP_HEADERS )

riscv/src/main.cpp

@@ -43,6 +43,7 @@
 #include <iss/jit/MCJIThelper.h>
 #include <iss/log_categories.h>
 #include <iss/plugin/instruction_count.h>
+#include <iss/plugin/cycle_estimate.h>
 
 namespace po = boost::program_options;
 
@@ -102,24 +103,19 @@ int main(int argc, char *argv[]) {
         // instantiate the simulator
         std::unique_ptr<iss::vm_if> vm{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
-        iss::plugin::instruction_count cc_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
+        iss::plugin::instruction_count ic_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
+        iss::plugin::cycle_estimate ce_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
         if (isa_opt.substr(0, 4)=="rv64") {
             iss::arch::rv64ia* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
             vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
         } else if (isa_opt.substr(0, 4)=="rv32") {
             iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
             vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
-//            vm->register_plugin(cc_plugin);
+            //vm->register_plugin(ce_plugin);
         } else {
             LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
             return 127;
         }
-        if (clim.count("elf"))
-            for (std::string input : clim["elf"].as<std::vector<std::string>>())
-                vm->get_arch()->load_file(input);
-        if (clim.count("mem"))
-            vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
-        for (std::string input : args) vm->get_arch()->load_file(input);// treat remaining arguments as elf files
         if (clim.count("disass")) {
             vm->setDisassEnabled(true);
             LOGGER(disass)::reporting_level() = logging::INFO;
@@ -130,19 +126,29 @@ int main(int argc, char *argv[]) {
                 LOGGER(disass)::print_severity() = false;
             }
         }
+        uint64_t start_address=0;
+        if (clim.count("mem"))
+             vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
+        if (clim.count("elf"))
+            for (std::string input : clim["elf"].as<std::vector<std::string>>()){
+            	auto start_addr = vm->get_arch()->load_file(input);
+            	if(start_addr.second)
+            		start_address=start_addr.first;
+            }
+        for (std::string input : args){
+        	auto start_addr = vm->get_arch()->load_file(input);// treat remaining arguments as elf files
+        	if(start_addr.second)
+        		start_address=start_addr.first;
+        }
         if (clim.count("reset")) {
             auto str = clim["reset"].as<std::string>();
-            auto start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), 0, 16) : std::stoull(str, 0, 10);
+            start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), 0, 16) : std::stoull(str, 0, 10);
-            vm->reset(start_address);
-        } else {
-            vm->reset();
         }
-        int64_t cycles = -1;
+		vm->reset(start_address);
-        cycles = clim["instructions"].as<int64_t>();
+        auto cycles = clim["instructions"].as<int64_t>();
         return vm->start(cycles, dump);
     } catch (std::exception &e) {
-        LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
+        LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
-                   << std::endl;
         return 2;
     }
 }

riscv/src/plugin/cycle_estimate.cpp

@@ -0,0 +1,89 @@
+/*******************************************************************************
+ * Copyright (C) 2017, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#include "iss/plugin/cycle_estimate.h"
+
+#include <iss/arch_if.h>
+#include <util/logging.h>
+#include <fstream>
+
+iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
+: arch_instr(nullptr)
+{
+    if (config_file_name.length() > 0) {
+        std::ifstream is(config_file_name);
+        if (is.is_open()) {
+            try {
+                is >> root;
+            } catch (Json::RuntimeError &e) {
+                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+            }
+        } else {
+            LOG(ERROR) << "Could not open input file " << config_file_name;
+        }
+    }
+}
+
+iss::plugin::cycle_estimate::~cycle_estimate() {
+}
+
+bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
+	arch_instr = vm.get_arch()->get_instrumentation_if();
+	const std::string  core_name = arch_instr->core_type_name();
+    Json::Value &val = root[core_name];
+    if(val.isArray()){
+    	delays.reserve(val.size());
+    	for(auto it:val){
+    		auto name = it["name"];
+    		auto size = it["size"];
+    		auto delay = it["delay"];
+    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
+    		if(delay.isUInt()){
+				delays.push_back(instr_desc{size.asUInt(), delay.asUInt(), 0});
+    		} else {
+				delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
+    		}
+    	}
+    }
+	return true;
+}
+
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
+	auto entry = delays[instr_info.instr_id];
+	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
+	if(taken && entry.taken > 1 ) // 1 is the default increment per instruction
+		arch_instr->set_curr_instr_cycles(entry.taken);
+	if(!taken && entry.not_taken > 1) // 1 is the default increment per instruction
+		arch_instr->set_curr_instr_cycles(entry.not_taken);
+}

riscv/src/plugin/instruction_count.cpp

@@ -32,7 +32,8 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#include "../../incl/iss/plugin/instruction_count.h"
+#include "iss/plugin/instruction_count.h"
+#include "iss/instrumentation_if.h"
 
 #include <iss/arch_if.h>
 #include <util/logging.h>
@@ -63,7 +64,7 @@ iss::plugin::instruction_count::~instruction_count() {
 }
 
 bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
-	const std::string  core_name = vm.get_arch()->core_type_name();
+	const std::string  core_name = vm.get_arch()->get_instrumentation_if()->core_type_name();
     Json::Value &val = root[core_name];
     if(val.isArray()){
     	delays.reserve(val.size());
@@ -85,6 +86,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
 	return true;
 }
 
-void iss::plugin::instruction_count::callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) {
+void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
-	rep_counts[instr_id]++;
+	rep_counts[instr_info.instr_id]++;
 }

sc-components

@@ -1 +1 @@
-Subproject commit 9d993c15a45b442aaad5a20c9b087c21ceac5b07
+Subproject commit ac8bd1d2912996c0ec526963f6f6bb862555402f