DBT-RISE/DBT-RISE-TGC
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Added ADC, H-Bridge and motor models, refactored project structure

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This commit is contained in:
Eyck Jentzsch
2018-07-28 09:45:49 +02:00
parent 100822810f
commit 38099e3fc6
61 changed files with 696 additions and 44 deletions
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158
platform/gen_input/aon.rdl Normal file
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regfile aon_regs {
// Watchdog Timer Registers
reg {
name = "wdogcfg";
desc = "Watchdog Timer Config Register";
field {
name="data";
} data[31:0];
} wdogcfg @0x00;
reg {
name ="wdogcount";
desc = "Watchdog Timer Count Registers";
field {
name="data";
} data[31:0];
} wdogcount @0x08;
reg {
name ="wdogs";
desc = "";
field {
name="data";
} data[31:0];
} wdogs @0x10;
reg {
name ="wdogfeed";
desc = "";
field {
name="data";
} data[31:0];
} wdogfeed @0x18;
reg {
name ="wdogkey";
desc = "";
field {
name="data";
} data[31:0];
} wdogkey @0x1C;
reg {
name ="wdogcmp";
desc = "";
field {
name="data";
} data[31:0];
} wdogcmp @0x20;
// Real-Time Clock Registers
reg {
name ="rtccfg";
desc = "";
field {
name="data";
} data[31:0];
} rtccfg @0x40;
reg {
name ="rtclo";
desc = "";
field {
name="data";
} data[31:0];
} rtclo @0x48;
reg {
name ="rtchi";
desc = "";
field {
name="data";
} data[31:0];
} rtchi @0x4C;
reg {
name ="rtcs";
desc = "";
field {
name="data";
} data[31:0];
} rtcs @0x50;
reg {
name ="rtccmp";
desc = "";
field {
name="data";
} data[31:0];
} rtccmp @0x60;
// AON Clock Configuration Registers
reg {
name ="lfrosccfg";
desc = "";
field {
name="data";
} data[31:0];
} lfrosccfg @0x70;
// Backup Registers
reg {
name ="lfrosccfg";
desc = "";
field {
name="data";
} data[31:0];
} backup[32] @0x80;
// Power Management Unit
reg {
name ="pmuwakeupi";
desc = "";
field {
name="delay";
} delay[3:0];
field {
name="vddpaden";
} vddpaden[5:5];
field {
name="corerst";
} corerst[7:7];
field {
name="hfclkrst";
} hfclkrst[8:8];
} pmuwakeupi[8] @0x0100;
reg {
name ="pmusleepi";
desc = "";
field {
name="delay";
} delay[3:0];
field {
name="vddpaden";
} vddpaden[5:5];
field {
name="corerst";
} corerst[7:7];
field {
name="hfclkrst";
} hfclkrst[8:8];
} pmusleepi[8] @0x0120;
reg {
name ="pmuie";
desc = "";
field {
name="data";
} data[31:0];
} pmuie @0x0140;
reg {
name ="pmucause";
desc = "";
field {
name="data";
} data[31:0];
} pmucause @0x0144;
reg {
name ="pmusleep";
desc = "";
field {
name="data";
} data[31:0];
} pmusleep @0x0148;
reg {
name ="pmukey";
desc = "";
field {
name="data";
} data[31:0];
} pmukey @0x014C;
};

27
platform/gen_input/clint.rdl Normal file
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regfile clint_regs {
reg {
name = "msip";
desc = "Hart 0 software interrupt register";
field {
name="msip";
} msip[0:0];
} msip @0;
reg {
name = "mtimecmp";
desc = "Hart 0 time comparator register";
regwidth=64;
field {
name="data";
fieldwidth=64;
} data = 64'h7FFFFFFFFFFFFFFF;
} mtimecmp @0x4000;
reg {
name = "mtime";
desc = "Timer register";
regwidth=64;
field {
fieldwidth=64;
name="data";
} data[63:0];
} mtime @0xBFF8;
};

24
platform/gen_input/fe310.rdl Normal file
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`include "gpio.rdl"
`include "uart.rdl"
`include "spi.rdl"
`include "plic.rdl"
`include "aon.rdl"
`include "prci.rdl"
`include "clint.rdl"
addrmap e300_plat_t {
lsb0;
clint_regs clint @0x02000000;
plic_regs plic @0x0C000000;
aon_regs aon @0x10000000;
prci_regs prci @0x10008000;
gpio_regs gpio0 @0x10012000;
uart_regs uart0 @0x10013000;
spi_regs qspi0 @0x10014000;
//pwm_regs pwm0 @0x10015000;
uart_regs uart1 @0x10023000;
spi_regs qspi1 @0x10024000;
//pwm_regs pwm1 @0x10025000;
spi_regs qspi2 @0x10034000;
//pwm_regs pwm2 @0x10035000;
} e300_plat;

121
platform/gen_input/gpio.rdl Normal file
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regfile gpio_regs {
reg {
name="value";
desc="pin value";
field {
name = "data";
} data[31:0];
} value @0x000;
reg {
name="input_en";
desc="* pin input enable";
field {
name = "data";
} data[31:0];
} input_en @0x004;
reg {
name="output_en";
desc="pin output enable";
field {
name = "data";
} data[31:0];
} output_en @0x008;
reg {
name="port";
desc="output port value";
field {
name = "data";
} data[31:0];
} port @0x00C;
reg {
name="pue";
desc="internal pull-up enable";
field {
name = "data";
} data[31:0];
} pue @0x010;
reg {
name="ds";
desc="Pin Drive Strength";
field {
name = "data";
} data[31:0];
} ds @0x014;
reg {
name="rise_ie";
desc="rise interrupt enable";
field {
name = "data";
} data[31:0];
} rise_ie @0x018;
reg {
name="rise_ip";
desc="rise interrupt pending";
field {
name = "data";
} data[31:0];
} rise_ip @0x01C;
reg {
name="fall_ie";
desc="fall interrupt enable";
field {
name = "data";
} data[31:0];
} fall_ie @0x020;
reg {
name="fall_ip";
desc="fall interrupt pending";
field {
name = "data";
} data[31:0];
} fall_ip @0x024;
reg {
name="high_ie";
desc="high interrupt enable";
field {
name = "data";
} data[31:0];
} high_ie @0x028;
reg {
name="high_ip";
desc="high interrupt pending";
field {
name = "data";
} data[31:0];
} high_ip @0x02C;
reg {
name="low_ie";
desc="low interrupt enable";
field {
name = "data";
} data[31:0];
} low_ie @0x030;
reg {
name="low_ip";
desc="low interrupt pending";
field {
name = "data";
} data[31:0];
} low_ip @0x034;
reg {
name="iof_en";
desc="HW I/O Function enable";
field {
name = "data";
} data[31:0];
} iof_en @0x038;
reg {
name="iof_sel";
desc="HW I/O Function select";
field {
name = "data";
} data[31:0];
} iof_sel @0x03C;
reg {
name="out_xor";
desc="Output XOR (invert)";
field {
name = "data";
} data[31:0];
} out_xor @0x040;
};

27
platform/gen_input/plic.rdl Normal file
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regfile plic_regs {
reg {
name="priority";
desc="interrupt source priority";
field {} priority[2:0];
} priority[256] @0x000;
reg {
name="pending";
desc="pending irq";
field {} pending[31:0];
} pending[8] @0x1000;
reg {
name="enabled";
desc="enabled interrupts";
field {} enabled[31:0];
} enabled[8] @0x2000;
reg {
name="threshold";
desc="interrupt priority threshold";
field {} \threshold[2:0];
} \threshold @0x200000;
reg {
name="claim/complete";
desc="interrupt handling completed";
field {} interrupt_claimed[31:0];
} claim_complete @0x200004;
};

41
platform/gen_input/prci.rdl Normal file
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regfile prci_regs {
reg {
name ="hfrosccfg";
desc = "";
field {} hfroscdiv[5:0];
field {} hfrosctrim[20:16];
field {} hfroscen[30:30];
field {} hfroscrdy[31:31];
} hfrosccfg @0x00;
reg {
name ="hfxosccfg";
desc = "";
field {} hfxoscrdy[31:31];
field {} hfxoscen[30:30];
} hfxosccfg @0x04;
reg {
name ="pllcfg";
desc = "";
field {} pllr[2:0];
field {} pllf[9:4];
field {} pllq[11:10];
field {} pllsel[16:16];
field {} pllrefsel[17:17];
field {} pllbypass[18:18];
field {} plllock[31:31];
} pllcfg @0x08;
reg {
name ="plloutdiv";
desc = "";
field {
name="data";
} data[31:0];
} plloutdiv @0x0c;
reg {
name ="coreclkcfg";
desc = "";
field {
name="data";
} data[31:0];
} coreclkcfg @0x10;
};

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platform/gen_input/spi.rdl Normal file
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regfile spi_regs {
reg {
name="sckdiv";
desc="Serial clock divisor";
field {
name ="div";
} div[12];
} sckdiv @0x000;
reg {
name="sckmode";
desc="Serial clock mode";
field {
name="pha";
} pha[1];
field {
name="pol";
} pol[1];
} sckmode @0x004;
reg {
name="csid";
desc="Chip select ID";
field {
name="csid";
} csid[32];
} csid @0x010;
reg {
name="csdef";
desc="Chip select default";
field {
name="csdef";
} csdef[32];
} csdef @0x014;
reg {
name="csmode";
desc="Chip select mode";
field {
name="mode";
} mode[2];
} csmode @0x018;
reg {
name="delay0";
desc="Delay control 0";
field {
name="cssck";
} cssck[7:0];
field {
name ="sckcs";
} sckcs[23:16];
} delay0 @0x028;
reg {
name="delay1";
desc="Delay control 1";
field {
name="intercs";
}intercs[15:0];
field {
name="interxfr";
} interxfr[23:16];
} delay1 @0x02C;
reg {
name="fmt";
desc="Frame format";
field{
name ="proto";
}proto[2];
field {
name="endian";
} endian[1];
field {
name="dir";
} dir[1];
field {
name="len";
} len[19:16];
} fmt @0x040;
reg {
name="txdata";
desc="Tx FIFO data";
field {
name="data";
} data[8];
field {
name="full";
} full[31:31];
} txdata @0x048;
reg {
name="rxdata";
desc="Rx FIFO data";
field{
name="data";
} data[8];
field{
name="empty";
} empty[31:31];
} rxdata @0x04C;
reg {
name="txmark";
desc="Tx FIFO watermark";
field {
name="txmark";
} txmark[3];
} txmark @0x050;
reg {
name="rxmark";
desc="Rx FIFO watermark";
field {
name="rxmark";
} rxmark[3];
} rxmark @0x054;
reg {
name="fctrl";
desc="SPI flash interface control";
field {
name="en";
} en[1];
} fctrl @0x060;
reg {
name="ffmt";
desc="SPI flash instruction format";
field {
name="cmd_en";
reset=0x1;
} cmd_en[1];
field {
name="addr_len";
reset=0x3;
} addr_len[2];
field {
name="pad_cnt";
reset=0x0;
} pad_cnt[4];
field {
name="cmd_proto";
reset=0x0;
} cmd_proto[2];
field {
name="addr_proto";
reset=0x0;
} addr_proto[2];
field {
name="data_proto";
reset=0x0;
} data_proto[2];
field {
name="cmd_code";
reset=0x3;
} cmd_code[23:16];
field {
name="pad_code";
reset=0x0;
} pad_code[8];
} ffmt @0x064;
reg {
name="ie";
desc="SPI interrupt enable";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ie @0x070;
reg {
name="ip";
desc="SPI interrupt pending";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ip @0x074;
};

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platform/gen_input/uart.rdl Normal file
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regfile uart_regs {
reg {
name="txdata";
desc="Transmit data register";
field {} data[7:0];
field {} full[31:31];
} txdata @0x00;
reg {
name="rxdata";
desc="Receive data register";
field {} data[7:0];
field {} empty[31:31];
}rxdata @0x04;
reg {
name="txctrl";
desc="Transmit control register";
field {} txen[1];
field {} nstop[1];
field {} txcnt[18:16];
}txctrl @0x08;
reg {
name="rxctrl";
desc="Receive control register";
field {} rxen[1];
field {} rxcnt[18:16];
}rxctrl @0x0C;
reg {
name="ie";
desc="UART interrupt enable";
field{} txwm[1];
field{} rxwm[1];
}ie @0x10;
reg {
name="ip";
desc="UART Interrupt pending";
field{} txwm[1];
field{} rxwm[1];
} ip @0x14;
reg {
name="div";
desc="Baud rate divisor";
field{} div[16];
} div @0x18;
};