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generate working ISS from CoreDSL 2.0

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This commit is contained in:
Eyck Jentzsch
2021-02-06 14:47:06 +00:00
parent da7e29fbb7
commit 34bb8e62ae
9 changed files with 2778 additions and 2398 deletions
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13
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -29,7 +29,14 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=64 // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
return regs
}
%>
#include "util/ities.h"
#include <util/logging.h>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
@ -41,8 +48,8 @@ using namespace iss::arch;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
reg.icount = 0;

32
gen_input/templates/interp/CORENAME.h.gtl
View File

@ -29,7 +29,24 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=pc.size // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
return regs
}
def getRegisterOffsets(){
def regs = registers.collect{it.offset}
def offs= regs[-1]
// append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT offsets starting with NEXT_PC size
[pc.size/8, 4, 4, 4, 4].each{ sz ->
regs+=offs+sz
offs+=sz
}
return regs
}
%>
#ifndef _${coreDef.name.toUpperCase()}_H_
#define _${coreDef.name.toUpperCase()}_H_
@ -61,7 +78,6 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
registers.each { reg -> %>
${reg.name},<%
}%>
NUM_REGS,
NEXT_${pc.name}=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
@ -80,11 +96,11 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${registers.size}> reg_bit_widths{
{${registers.collect{it.size}.join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
{${getRegisterSizes().join(',')}}};
static constexpr std::array<const uint32_t, ${registers.size}> reg_byte_offsets{
{${registers.collect{it.offset}.join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
{${getRegisterOffsets().join(',')}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -137,9 +153,9 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
protected:
struct ${coreDef.name}_regs {<%
registers.each { reg ->%>
registers.each { reg -> if(reg.size>0) {%>
uint${reg.size}_t ${reg.name} = 0;<%
}%>
}}%>
uint${pc.size}_t NEXT_${pc.name} = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;

47
gen_input/templates/interp/vm_CORENAME.cpp.gtl
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@ -185,27 +185,32 @@ private:
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, ${idx});
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */
<%instr.disass.eachLine{%>${it}
<%}%>}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + ${instr.length/8};
uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::X0);
uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::PC);
<%instr.behavior.eachLine{%>${it}
<%}%>this->do_sync(POST_SYNC, ${idx});
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
// pre execution stuff
this->do_sync(PRE_SYNC, ${idx});
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */
<%instr.disass.eachLine{%>${it}
<%}%>
}
// prepare execution
uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
<%instr.behavior.eachLine{%>${it}
<%}%>// post execution stuff<% if(instr.modifiesPC) { %>
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);<% } else { %>
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + ${instr.length/8};<% } %>
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
<%}%>
/****************************************************************************