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applies clang format

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This commit is contained in:
Eyck Jentzsch
2025-03-16 14:38:45 +01:00
parent 63d0162119
commit 31c6bb55f4
12 changed files with 81 additions and 102 deletions
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35
src/iss/mem/mmu.h
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@@ -32,10 +32,10 @@
* eyck@minres.com - initial implementation
******************************************************************************/
#include "memory_if.h"
#include "iss/arch/riscv_hart_common.h"
#include "iss/vm_types.h"
#include <util/logging.h>
#include "../mem/memory_if.h"
namespace iss {
namespace mem {
@@ -54,7 +54,6 @@ enum {
PTE_SOFT = 0x300 // Reserved for Software
};
template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
struct vm_info {
@@ -106,7 +105,7 @@ inline void write_reg_with_offset(uint32_t& reg, uint8_t offs, const uint8_t* co
break;
}
}
//TODO: update vminfo on trap enter and leave as well as mstatus write, reset
// TODO: update vminfo on trap enter and leave as well as mstatus write, reset
template <typename WORD_TYPE> struct mmu : public memory_elem {
using this_class = mmu<WORD_TYPE>;
using reg_t = WORD_TYPE;
@@ -115,13 +114,11 @@ template <typename WORD_TYPE> struct mmu : public memory_elem {
constexpr static reg_t PGSIZE = 1 << PGSHIFT;
constexpr static reg_t PGMASK = PGSIZE - 1;
mmu(arch::priv_if<WORD_TYPE> hart_if)
: hart_if(hart_if) {
hart_if.csr_rd_cb[satp] = MK_CSR_RD_CB(read_satp);
hart_if.csr_wr_cb[satp] = MK_CSR_WR_CB(write_satp);
}
}
virtual ~mmu() = default;
@@ -156,7 +153,7 @@ private:
auto len1 = split_addr - addr;
auto res = down_stream_mem.wr_mem(access, addr, len1, data);
if(res == iss::Ok)
res = down_stream_mem.wr_mem(access, split_addr, length - len1, data + len1);
res = down_stream_mem.wr_mem(access, split_addr, length - len1, data + len1);
return res;
}
}
@@ -177,9 +174,9 @@ private:
iss::status read_satp(unsigned addr, reg_t& val) {
auto tvm = bit_sub<20, 1>(hart_if.state.mstatus());
if(hart_if.PRIV == arch::PRIV_S & tvm != 0) {
hart_if.raise_trap(2, 0, hart_if.PC);
// hart_if.reg.trap_state = (1 << 31) | (2 << 16);
// hart_if.fault_data = hart_if.reg.PC;
hart_if.raise_trap(2, 0, hart_if.PC);
// hart_if.reg.trap_state = (1 << 31) | (2 << 16);
// hart_if.fault_data = hart_if.reg.PC;
return iss::Err;
}
val = satp;
@@ -189,9 +186,9 @@ private:
iss::status write_satp(unsigned addr, reg_t val) {
reg_t tvm = hart_if.state.mstatus.TVM;
if(hart_if.PRIV == arch::PRIV_S & tvm != 0) {
hart_if.raise_trap(2, 0, hart_if.PC);
// hart_if.reg.trap_state = (1 << 31) | (2 << 16);
// hart_if.fault_data = hart_if.reg.PC;
hart_if.raise_trap(2, 0, hart_if.PC);
// hart_if.reg.trap_state = (1 << 31) | (2 << 16);
// hart_if.fault_data = hart_if.reg.PC;
return iss::Err;
}
satp = val;
@@ -249,7 +246,7 @@ protected:
memory_if down_stream_mem;
};
template <typename WORD_TYPE> uint64_t mmu<WORD_TYPE>::virt2phys(iss::access_type access, uint64_t addr) {
template <typename WORD_TYPE> uint64_t mmu<WORD_TYPE>::virt2phys(iss::access_type access, uint64_t addr) {
const auto type = access & iss::access_type::FUNC;
auto it = ptw.find(addr >> PGSHIFT);
if(it != ptw.end()) {
@@ -268,8 +265,8 @@ template <typename WORD_TYPE> uint64_t mmu<WORD_TYPE>::virt2phys(iss::access_ty
#endif
} else {
uint32_t mode = type != iss::access_type::FETCH && hart_if.state.mstatus.MPRV ? // MPRV
hart_if.state.mstatus.MPP
: hart_if.PRIV;
hart_if.state.mstatus.MPP
: hart_if.PRIV;
const vm_info& vm = vmt[static_cast<uint16_t>(type) / 2];
@@ -279,7 +276,7 @@ template <typename WORD_TYPE> uint64_t mmu<WORD_TYPE>::virt2phys(iss::access_ty
// verify bits xlen-1:va_bits-1 are all equal
const int va_bits = PGSHIFT + vm.levels * vm.idxbits;
const reg_t mask = (reg_t(1) << (sizeof(reg_t)*8 - (va_bits - 1))) - 1;
const reg_t mask = (reg_t(1) << (sizeof(reg_t) * 8 - (va_bits - 1))) - 1;
const reg_t masked_msbs = (addr >> (va_bits - 1)) & mask;
const int levels = (masked_msbs != 0 && masked_msbs != mask) ? 0 : vm.levels;
@@ -290,8 +287,7 @@ template <typename WORD_TYPE> uint64_t mmu<WORD_TYPE>::virt2phys(iss::access_ty
// check that physical address of PTE is legal
reg_t pte = 0;
const uint8_t res = down_stream_mem.rd_mem(iss::access_type::READ, base + idx * vm.ptesize, vm.ptesize,
(uint8_t*)&pte);
const uint8_t res = down_stream_mem.rd_mem(iss::access_type::READ, base + idx * vm.ptesize, vm.ptesize, (uint8_t*)&pte);
if(res != 0)
throw arch::trap_load_access_fault(addr);
const reg_t ppn = pte >> PTE_PPN_SHIFT;
@@ -353,6 +349,5 @@ template <typename WORD_TYPE> inline void mmu<WORD_TYPE>::update_vm_info() {
ptw.clear();
}
} // namespace mem
} // namespace iss