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extends factory to support SystemC core wrapper

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This commit is contained in:
Eyck Jentzsch
2023-07-06 08:02:48 +02:00
parent a20eab0c2b
commit 2f8ee6e89d
9 changed files with 325 additions and 54 deletions
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21
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -34,10 +34,9 @@ def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
%>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <util/logging.h>
@ -315,3 +314,21 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
}
} // namespace interp
} // namespace iss
#include <iss/factory.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
}),
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
})
};
}
}

21
gen_input/templates/tcc/CORENAME.cpp.gtl
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@ -31,7 +31,6 @@
*******************************************************************************/
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
@ -310,5 +309,23 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
}
} // namesapce tcc
} // namespace iss
#include <iss/factory.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
}),
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
})
};
}
}