Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop

src/iss/arch/riscv_hart_m_p.h

@@ -293,7 +293,7 @@ public:
 
     void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
 
-    void set_semihosting_callback(std::function<void(arch_if*, reg_t, reg_t)>& cb) { semihosting_cb = cb; };
+    void set_semihosting_callback(semihosting_cb_t<reg_t>  cb) { semihosting_cb = cb; };
 
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
@@ -354,7 +354,7 @@ protected:
     bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
-    std::function<void(arch_if*, reg_t, reg_t)> semihosting_cb;
+    semihosting_cb_t<reg_t>  semihosting_cb;
 
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
@@ -1272,7 +1272,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
 #endif
                     CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred ";
 
-                    semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/);
+                    semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/);
                     return this->reg.NEXT_PC;
                 }
             }

src/iss/arch/riscv_hart_mu_p.h

@@ -319,7 +319,7 @@ public:
 
     void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
 
-    void set_semihosting_callback(std::function<void(arch_if*, reg_t, reg_t)>& cb) { semihosting_cb = cb; };
+    void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
 
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
@@ -380,7 +380,7 @@ protected:
     bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
-    std::function<void(arch_if*, reg_t, reg_t)> semihosting_cb;
+    semihosting_cb_t<reg_t>  semihosting_cb;
 
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
@@ -1507,7 +1507,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
 #endif
                     CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred ";
 
-                    semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/);
+                    semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/);
                     return this->reg.NEXT_PC;
                 }
             }

src/iss/semihosting/semihosting.cpp

@@ -1,16 +1,61 @@
 #include "semihosting.h"
 #include <cstdint>
+#include <map>
 #include <iss/vm_types.h>
 #include <stdexcept>
+#include <chrono>
 // explanation of syscalls can be found at https://github.com/SpinalHDL/openocd_riscv/blob/riscv_spinal/src/target/semihosting_common.h
-template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter) {
+
-    switch(static_cast<semihosting_syscalls>(call_number)) {
+const char *SYS_OPEN_MODES_STRS[] = { "r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b" };
+
+template <typename T> T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len=4) {
+    uint8_t bytes[4];
+    auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr, 4, &bytes[0]);
+    //auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+
+    if(res != iss::Ok){
+        return 0; //TODO THROW ERROR
+    } else return static_cast<T>(bytes[0]) | (static_cast<T>(bytes[1]) << 8) | (static_cast<T>(bytes[2]) << 16) | (static_cast<T>(bytes[3]) << 24);
+}
+
+template <typename T> std::string sh_read_string(iss::arch_if* arch_if_ptr, T addr, T str_len){
+    std::vector<uint8_t> buffer(str_len);
+    for (int i = 0; i < str_len; i++ ) {
+        buffer[i] = sh_read_field(arch_if_ptr, addr + i, 1);
+    }
+    std::string str(buffer.begin(), buffer.end());
+    return str;
+}
+
+
+template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter) {
+    static std::map<T, FILE *> openFiles;
+    static T file_count = 3;
+    static T semihostingErrno;
+
+    switch(static_cast<semihosting_syscalls>(*call_number)) {
     case semihosting_syscalls::SYS_CLOCK: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        auto end = std::chrono::high_resolution_clock::now(); // end measurement 
+        auto elapsed = end - timeVar;
+        auto millis = std::chrono::duration_cast<std::chrono::milliseconds>(elapsed).count();
+        *call_number = millis; //TODO get time now
         break;
     }
     case semihosting_syscalls::SYS_CLOSE: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T file_handle = *parameter;
+        if (openFiles.size() <= file_handle && file_handle < 0) {
+            semihostingErrno = EBADF;
+            return;
+        }
+        auto file = openFiles[file_handle];
+        openFiles.erase(file_handle);
+        if (!(file == stdin || file == stdout || file == stderr)) {
+            int i = fclose(file);
+            *call_number = i;
+        } else {
+            *call_number = -1;
+            semihostingErrno = EINTR;
+        }
         break;
     }
     case semihosting_syscalls::SYS_ELAPSED: {
@@ -18,7 +63,7 @@ template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T cal
         break;
     }
     case semihosting_syscalls::SYS_ERRNO: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        *call_number = semihostingErrno;
         break;
     }
     case semihosting_syscalls::SYS_EXIT: {
@@ -31,7 +76,15 @@ template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T cal
         break;
     }
     case semihosting_syscalls::SYS_FLEN: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T file_handle = *parameter;
+        auto file = openFiles[file_handle];
+
+        size_t currentPos = ftell(file);
+        if (currentPos < 0) throw std::runtime_error("SYS_FLEN negative value");
+        fseek(file, 0, SEEK_END);
+        size_t length = ftell(file);
+        fseek(file, currentPos, SEEK_SET);
+        *call_number = (T)length;
         break;
     }
     case semihosting_syscalls::SYS_GET_CMDLINE: {
@@ -43,39 +96,127 @@ template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T cal
         break;
     }
     case semihosting_syscalls::SYS_ISERROR: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T value = *parameter;
+        *call_number = (value != 0);
         break;
     }
     case semihosting_syscalls::SYS_ISTTY: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T file_handle = *parameter;       
+        *call_number = (file_handle == 0 || file_handle == 1 || file_handle == 2);
         break;
     }
     case semihosting_syscalls::SYS_OPEN: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T mode = sh_read_field<T>(arch_if_ptr, 4+(*parameter));
+        T path_len = sh_read_field<T>(arch_if_ptr, 8+(*parameter));
+
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        //TODO LOG INFO
+
+        if (mode >= 12) {
+            //TODO throw ERROR
+            return;
+        }
+
+        FILE *file = nullptr;
+        if(path_str == ":tt") {
+            if (mode < 4)
+                file = stdin;
+            else if (mode < 8) 
+                file = stdout;
+            else 
+                file = stderr;
+        } else {
+            file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]);
+            if (file == nullptr) {
+                //TODO throw error
+                return;
+            }
+        }
+        T file_handle = file_count++;
+        openFiles[file_handle] = file;
+        *call_number = file_handle;
         break;
+
     }
     case semihosting_syscalls::SYS_READ: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter)+4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter)+8);
+
+        auto file = openFiles[file_handle];
+
+        std::vector<uint8_t> buffer(count);
+        size_t num_read = 0;
+        if (file == stdin)
+        {
+            // when reading from stdin: mimic behaviour from read syscall
+            // and return on newline.
+            while (num_read < count)
+            {
+                char c = fgetc(file);
+                buffer[num_read] = c;
+                num_read++;
+                if (c == '\n')
                     break;
             }
+        } else {
+            num_read = fread(buffer.data(), 1, count, file);
+        }
+        buffer.resize(num_read);
+        for(int i  = 0; i<num_read; i++) {
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr+i, 1, &buffer[i]);
+            if(res != iss::Ok)
+                return;
+        }
+        *call_number = count - num_read;
+        break;
+
+    }
     case semihosting_syscalls::SYS_READC: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        uint8_t character = getchar();
+        //character = getchar();
+        /*if(character != iss::Ok)
+            std::cout << "Not OK";
+            return;*/
+        *call_number = character;
         break;
     }
     case semihosting_syscalls::SYS_REMOVE: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len = sh_read_field<T>(arch_if_ptr, (*parameter)+4);
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        if(remove(path_str.c_str())<0) *call_number = -1;
         break;
     }
     case semihosting_syscalls::SYS_RENAME: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T path_str_addr_old = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len_old = sh_read_field<T>(arch_if_ptr, (*parameter)+4);
+        T path_str_addr_new = sh_read_field<T>(arch_if_ptr, (*parameter)+8);
+        T path_len_new = sh_read_field<T>(arch_if_ptr, (*parameter)+12);
+
+        std::string path_str_old = sh_read_string<T>(arch_if_ptr, path_str_addr_old, path_len_old);
+        std::string path_str_new = sh_read_string<T>(arch_if_ptr, path_str_addr_new, path_len_new); 
+        rename(path_str_old.c_str(), path_str_new.c_str());       
         break;
     }
     case semihosting_syscalls::SYS_SEEK: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T file_handle = sh_read_field<T>(arch_if_ptr, *parameter);
+        T pos = sh_read_field<T>(arch_if_ptr, (*parameter)+1);
+        auto file = openFiles[file_handle];
+
+        int retval = fseek(file, pos, SEEK_SET);
+        if(retval<0) throw std::runtime_error("SYS_SEEK negative return value");
+
         break;
     }
     case semihosting_syscalls::SYS_SYSTEM: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T cmd_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T cmd_len = sh_read_field<T>(arch_if_ptr, (*parameter)+1); 
+        std::string cmd = sh_read_string<T>(arch_if_ptr, cmd_addr, cmd_len);
+        system(cmd.c_str());
         break;
     }
     case semihosting_syscalls::SYS_TICKFREQ: {
@@ -83,20 +224,43 @@ template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T cal
         break;
     }
     case semihosting_syscalls::SYS_TIME: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        //returns time in seconds scince 01.01.1970 00:00
+        *call_number = time(NULL);
         break;
     }
     case semihosting_syscalls::SYS_TMPNAM: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T buffer_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T identifier = sh_read_field<T>(arch_if_ptr, (*parameter)+1);
+        T buffer_len = sh_read_field<T>(arch_if_ptr, (*parameter)+2);
+
+        if (identifier > 255) {
+            *call_number = -1;
+            return;
+        }
+        std::stringstream ss;
+        ss << "tmp/file-" << std::setfill('0') << std::setw(3) << identifier;
+        std::string filename = ss.str();
+
+        for(int i = 0; i < buffer_len; i++) {
+            uint8_t character = filename[i];
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter)+i, 1, &character);
+            if(res != iss::Ok) return;
+        }
         break;
     }
     case semihosting_syscalls::SYS_WRITE: {
-        throw std::runtime_error("Semihosting Call not Implemented");
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter)+4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter)+8);
+
+        auto file = openFiles[file_handle];
+        std::string str = sh_read_string<T>(arch_if_ptr, addr, count);
+        fwrite(&str[0], 1, count, file);
         break;
     }
     case semihosting_syscalls::SYS_WRITEC: {
         uint8_t character;
-        auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, parameter, 1, &character);
+        auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
         if(res != iss::Ok)
             return;
         putchar(character);
@@ -105,13 +269,13 @@ template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T cal
     case semihosting_syscalls::SYS_WRITE0: {
         uint8_t character;
         while(1) {
-            auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, parameter, 1, &character);
+            auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
             if(res != iss::Ok)
                 return;
             if(character == 0)
                 break;
             putchar(character);
-            parameter++;
+            (*parameter)++;
         }
         break;
     }
@@ -128,5 +292,5 @@ template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T cal
         break;
     }
 }
-template void semihosting_callback<uint32_t>(iss::arch_if* arch_if_ptr, uint32_t call_number, uint32_t parameter);
+template class semihosting_callback<uint32_t>;
-template void semihosting_callback<uint64_t>(iss::arch_if* arch_if_ptr, uint64_t call_number, uint64_t parameter);
+template class semihosting_callback<uint64_t>;

src/iss/semihosting/semihosting.h

@@ -1,6 +1,8 @@
 #ifndef _SEMIHOSTING_H_
 #define _SEMIHOSTING_H_
 #include <iss/arch_if.h>
+#include <functional>
+#include <chrono>
 /*
  * According to:
  * "Semihosting for AArch32 and AArch64, Release 2.0"
@@ -48,6 +50,11 @@ enum class semihosting_syscalls {
     USER_CMD_0x1FF = 0x1FF,
 };
 
-template <typename T> void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter);
+template <typename T> struct semihosting_callback{
+    std::chrono::high_resolution_clock::time_point timeVar;
+    semihosting_callback(): timeVar(std::chrono::high_resolution_clock::now()) {}
+    void operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter);
+};
 
+template <typename T> using semihosting_cb_t = std::function<void(iss::arch_if*, T*, T*)>;
 #endif

src/main.cpp

@@ -119,7 +119,8 @@ int main(int argc, char* argv[]) {
         // instantiate the simulator
         iss::vm_ptr vm{nullptr};
         iss::cpu_ptr cpu{nullptr};
-        std::function<void(iss::arch_if*, uint32_t, uint32_t)> semihosting_cb = &semihosting_callback<uint32_t>;
+        semihosting_callback<uint32_t> cb{}; 
+        semihosting_cb_t<uint32_t> semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) {cb(i,a0,a1);};
         std::string isa_opt(clim["isa"].as<std::string>());
         if(isa_opt.size() == 0 || isa_opt == "?") {
             auto list = f.get_names();

src/vm/asmjit/vm_tgc5c.cpp

@@ -4795,7 +4795,7 @@ volatile std::array<bool, 2> dummy = {
 		    auto vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
                 cpu->set_semihosting_callback(*cb);
             }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
@@ -4805,7 +4805,7 @@ volatile std::array<bool, 2> dummy = {
 		    auto vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
                 cpu->set_semihosting_callback(*cb);
             }
             return {cpu_ptr{cpu}, vm_ptr{vm}};

src/vm/interp/vm_tgc5c.cpp

@@ -2700,7 +2700,7 @@ volatile std::array<bool, 2> dummy = {
 		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
                 cpu->set_semihosting_callback(*cb);
             }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
@@ -2710,7 +2710,7 @@ volatile std::array<bool, 2> dummy = {
 		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
                 cpu->set_semihosting_callback(*cb);
             }
             return {cpu_ptr{cpu}, vm_ptr{vm}};

src/vm/tcc/vm_tgc5c.cpp

@@ -3653,7 +3653,7 @@ volatile std::array<bool, 2> dummy = {
 		    auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
                 cpu->set_semihosting_callback(*cb);
             }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
@@ -3663,7 +3663,7 @@ volatile std::array<bool, 2> dummy = {
 		    auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
                 cpu->set_semihosting_callback(*cb);
             }
             return {cpu_ptr{cpu}, vm_ptr{vm}};

src_test/iss/arch/tgc5a.cpp

@@ -0,0 +1,70 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+// clang-format off
+#include "tgc5a.h"
+#include "util/ities.h"
+#include <util/logging.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, 20>    iss::arch::traits<iss::arch::tgc5a>::reg_names;
+constexpr std::array<const char*, 20>    iss::arch::traits<iss::arch::tgc5a>::reg_aliases;
+constexpr std::array<const uint32_t, 27> iss::arch::traits<iss::arch::tgc5a>::reg_bit_widths;
+constexpr std::array<const uint32_t, 27> iss::arch::traits<iss::arch::tgc5a>::reg_byte_offsets;
+
+tgc5a::tgc5a()  = default;
+
+tgc5a::~tgc5a() = default;
+
+void tgc5a::reset(uint64_t address) {
+    auto base_ptr = reinterpret_cast<traits<tgc5a>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc5a>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.PRIV=0x3;
+    reg.trap_state=0;
+    reg.icount=0;
+}
+
+uint8_t *tgc5a::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+tgc5a::phys_addr_t tgc5a::virt2phys(const iss::addr_t &addr) {
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5a>::addr_mask);
+}
+// clang-format on

src_test/iss/arch/tgc5a.h

@@ -0,0 +1,209 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _TGC5A_H_
+#define _TGC5A_H_
+// clang-format off
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgc5a;
+
+template <> struct traits<tgc5a> {
+
+    constexpr static char const* const core_type = "TGC5A";
+    
+    static constexpr std::array<const char*, 20> reg_names{
+        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "pc", "next_pc", "priv", "dpc"}};
+ 
+    static constexpr std::array<const char*, 20> reg_aliases{
+        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "pc", "next_pc", "priv", "dpc"}};
+
+    enum constants {MISA_VAL=1073741840ULL, MARCHID_VAL=2147483649ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=16ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+    static constexpr std::array<const uint32_t, 27> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
+
+    static constexpr std::array<const uint32_t, 27> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,73,77,81,85,93,101,109,113}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, FENCE, RES, CSR };
+    
+    enum class opcode_e {
+        LUI = 0,
+        AUIPC = 1,
+        JAL = 2,
+        JALR = 3,
+        BEQ = 4,
+        BNE = 5,
+        BLT = 6,
+        BGE = 7,
+        BLTU = 8,
+        BGEU = 9,
+        LB = 10,
+        LH = 11,
+        LW = 12,
+        LBU = 13,
+        LHU = 14,
+        SB = 15,
+        SH = 16,
+        SW = 17,
+        ADDI = 18,
+        SLTI = 19,
+        SLTIU = 20,
+        XORI = 21,
+        ORI = 22,
+        ANDI = 23,
+        SLLI = 24,
+        SRLI = 25,
+        SRAI = 26,
+        ADD = 27,
+        SUB = 28,
+        SLL = 29,
+        SLT = 30,
+        SLTU = 31,
+        XOR = 32,
+        SRL = 33,
+        SRA = 34,
+        OR = 35,
+        AND = 36,
+        FENCE = 37,
+        ECALL = 38,
+        EBREAK = 39,
+        MRET = 40,
+        WFI = 41,
+        CSRRW = 42,
+        CSRRS = 43,
+        CSRRC = 44,
+        CSRRWI = 45,
+        CSRRSI = 46,
+        CSRRCI = 47,
+        FENCE_I = 48,
+        MAX_OPCODE
+    };
+};
+
+struct tgc5a: public arch_if {
+
+    using virt_addr_t = typename traits<tgc5a>::virt_addr_t;
+    using phys_addr_t = typename traits<tgc5a>::phys_addr_t;
+    using reg_t =  typename traits<tgc5a>::reg_t;
+    using addr_t = typename traits<tgc5a>::addr_t;
+
+    tgc5a();
+    ~tgc5a();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+
+#pragma pack(push, 1)
+    struct TGC5A_regs { 
+        uint32_t X0 = 0; 
+        uint32_t X1 = 0; 
+        uint32_t X2 = 0; 
+        uint32_t X3 = 0; 
+        uint32_t X4 = 0; 
+        uint32_t X5 = 0; 
+        uint32_t X6 = 0; 
+        uint32_t X7 = 0; 
+        uint32_t X8 = 0; 
+        uint32_t X9 = 0; 
+        uint32_t X10 = 0; 
+        uint32_t X11 = 0; 
+        uint32_t X12 = 0; 
+        uint32_t X13 = 0; 
+        uint32_t X14 = 0; 
+        uint32_t X15 = 0; 
+        uint32_t PC = 0; 
+        uint32_t NEXT_PC = 0; 
+        uint8_t PRIV = 0; 
+        uint32_t DPC = 0;
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
+    } reg;
+#pragma pack(pop)
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+    uint32_t get_fcsr(){return 0;}
+    void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGC5A_H_ */
+// clang-format on

src_test/iss/arch/tgc5b.cpp

@@ -0,0 +1,70 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+// clang-format off
+#include "tgc5b.h"
+#include "util/ities.h"
+#include <util/logging.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5b>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5b>::reg_aliases;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5b>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5b>::reg_byte_offsets;
+
+tgc5b::tgc5b()  = default;
+
+tgc5b::~tgc5b() = default;
+
+void tgc5b::reset(uint64_t address) {
+    auto base_ptr = reinterpret_cast<traits<tgc5b>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc5b>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.PRIV=0x3;
+    reg.trap_state=0;
+    reg.icount=0;
+}
+
+uint8_t *tgc5b::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+tgc5b::phys_addr_t tgc5b::virt2phys(const iss::addr_t &addr) {
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5b>::addr_mask);
+}
+// clang-format on

src_test/iss/arch/tgc5b.h

@@ -0,0 +1,225 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _TGC5B_H_
+#define _TGC5B_H_
+// clang-format off
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgc5b;
+
+template <> struct traits<tgc5b> {
+
+    constexpr static char const* const core_type = "TGC5B";
+    
+    static constexpr std::array<const char*, 36> reg_names{
+        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
+ 
+    static constexpr std::array<const char*, 36> reg_aliases{
+        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
+
+    enum constants {MISA_VAL=1073742080ULL, MARCHID_VAL=2147483650ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+    static constexpr std::array<const uint32_t, 43> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
+
+    static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, FENCE, RES, CSR };
+    
+    enum class opcode_e {
+        LUI = 0,
+        AUIPC = 1,
+        JAL = 2,
+        JALR = 3,
+        BEQ = 4,
+        BNE = 5,
+        BLT = 6,
+        BGE = 7,
+        BLTU = 8,
+        BGEU = 9,
+        LB = 10,
+        LH = 11,
+        LW = 12,
+        LBU = 13,
+        LHU = 14,
+        SB = 15,
+        SH = 16,
+        SW = 17,
+        ADDI = 18,
+        SLTI = 19,
+        SLTIU = 20,
+        XORI = 21,
+        ORI = 22,
+        ANDI = 23,
+        SLLI = 24,
+        SRLI = 25,
+        SRAI = 26,
+        ADD = 27,
+        SUB = 28,
+        SLL = 29,
+        SLT = 30,
+        SLTU = 31,
+        XOR = 32,
+        SRL = 33,
+        SRA = 34,
+        OR = 35,
+        AND = 36,
+        FENCE = 37,
+        ECALL = 38,
+        EBREAK = 39,
+        MRET = 40,
+        WFI = 41,
+        CSRRW = 42,
+        CSRRS = 43,
+        CSRRC = 44,
+        CSRRWI = 45,
+        CSRRSI = 46,
+        CSRRCI = 47,
+        FENCE_I = 48,
+        MAX_OPCODE
+    };
+};
+
+struct tgc5b: public arch_if {
+
+    using virt_addr_t = typename traits<tgc5b>::virt_addr_t;
+    using phys_addr_t = typename traits<tgc5b>::phys_addr_t;
+    using reg_t =  typename traits<tgc5b>::reg_t;
+    using addr_t = typename traits<tgc5b>::addr_t;
+
+    tgc5b();
+    ~tgc5b();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+
+#pragma pack(push, 1)
+    struct TGC5B_regs { 
+        uint32_t X0 = 0; 
+        uint32_t X1 = 0; 
+        uint32_t X2 = 0; 
+        uint32_t X3 = 0; 
+        uint32_t X4 = 0; 
+        uint32_t X5 = 0; 
+        uint32_t X6 = 0; 
+        uint32_t X7 = 0; 
+        uint32_t X8 = 0; 
+        uint32_t X9 = 0; 
+        uint32_t X10 = 0; 
+        uint32_t X11 = 0; 
+        uint32_t X12 = 0; 
+        uint32_t X13 = 0; 
+        uint32_t X14 = 0; 
+        uint32_t X15 = 0; 
+        uint32_t X16 = 0; 
+        uint32_t X17 = 0; 
+        uint32_t X18 = 0; 
+        uint32_t X19 = 0; 
+        uint32_t X20 = 0; 
+        uint32_t X21 = 0; 
+        uint32_t X22 = 0; 
+        uint32_t X23 = 0; 
+        uint32_t X24 = 0; 
+        uint32_t X25 = 0; 
+        uint32_t X26 = 0; 
+        uint32_t X27 = 0; 
+        uint32_t X28 = 0; 
+        uint32_t X29 = 0; 
+        uint32_t X30 = 0; 
+        uint32_t X31 = 0; 
+        uint32_t PC = 0; 
+        uint32_t NEXT_PC = 0; 
+        uint8_t PRIV = 0; 
+        uint32_t DPC = 0;
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
+    } reg;
+#pragma pack(pop)
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+    uint32_t get_fcsr(){return 0;}
+    void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGC5B_H_ */
+// clang-format on