DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

extends factory to support SystemC core wrapper

Browse Source
This commit is contained in:
Eyck Jentzsch
2023-07-06 08:02:48 +02:00
parent 7b31b8ca8e
commit 250ea3c980
11 changed files with 380 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
src/vm/interp/vm_tgc_c.cpp
View File

@@ -30,10 +30,9 @@
*
*******************************************************************************/
#include <iss/arch/tgc_c.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/arch/tgc_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <util/logging.h>
@@ -1731,7 +1730,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@@ -1759,7 +1758,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
if(rd != 0) {
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
@@ -1787,7 +1786,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
int64_t res = (int32_t)*(X+rs1) * *(X+rs2);
int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2));
if(rd != 0) {
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
@@ -1815,7 +1814,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint64_t res = *(X+rs1) * *(X+rs2);
uint64_t res = (uint64_t)((uint64_t)*(X+rs1) * (uint64_t)*(X+rs2));
if(rd != 0) {
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
@@ -2013,8 +2012,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
uint32_t load_address = (uint32_t)(*(X+rs1 + 8) + uimm);
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm);
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLW;
*(X+rd + 8) = (uint32_t)(int32_t)read_res;
}
@@ -2036,8 +2035,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
uint32_t load_address = (uint32_t)(*(X+rs1 + 8) + uimm);
super::template write_mem<uint32_t>(traits::MEM, load_address, (uint32_t)*(X+rs2 + 8));
uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm);
super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 + 8));
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSW;
}
TRAP_CSW:break;
@@ -2438,8 +2437,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint32_t offs = (uint32_t)(*(X+2) + uimm);
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLWSP;
int32_t res = (int32_t)read_res;
*(X+rd) = (uint32_t)res;
*(X+rd) = (uint32_t)(int32_t)read_res;
}
}
TRAP_CLWSP:break;
@@ -2647,3 +2645,30 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
}
} // namespace interp
} // namespace iss
#include <iss/factory.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
std::array<bool, 2> dummy = {
core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})
};
}
}
extern "C" {
bool* get_tgc_c_interp_creators() {
return iss::dummy.data();
}
}

49
src/vm/tcc/vm_tgc_c.cpp
View File

@@ -31,7 +31,6 @@
*******************************************************************************/
#include <iss/arch/tgc_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
@@ -2024,7 +2023,7 @@ private:
this->gen_raise_trap(tu, 0, 2);
}
else{
auto res = tu.assignment(tu.mul(tu.ext(tu.load(rs1+ traits::X0, 0),32,false),tu.ext(tu.load(rs2+ traits::X0, 0),32,false)),64);
auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,false),tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,false))),64,false),64);
if(rd!=0) {
tu.store(rd + traits::X0,tu.ext(res,32,true));
}
@@ -2058,7 +2057,7 @@ private:
this->gen_raise_trap(tu, 0, 2);
}
else{
auto res = tu.assignment(tu.mul(tu.ext(tu.load(rs1+ traits::X0, 0),32,false),tu.ext(tu.load(rs2+ traits::X0, 0),32,false)),64);
auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,false),tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,false))),64,false),64);
if(rd!=0) {
tu.store(rd + traits::X0,tu.ext((tu.lshr(res,tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,true));
}
@@ -2092,7 +2091,7 @@ private:
this->gen_raise_trap(tu, 0, 2);
}
else{
auto res = tu.assignment(tu.mul(tu.ext(tu.load(rs1+ traits::X0, 0),32,false),tu.load(rs2+ traits::X0, 0)),64);
auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,false),tu.ext(tu.load(rs2+ traits::X0, 0),64,true))),64,false),64);
if(rd!=0) {
tu.store(rd + traits::X0,tu.ext((tu.lshr(res,tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,true));
}
@@ -2126,7 +2125,7 @@ private:
this->gen_raise_trap(tu, 0, 2);
}
else{
auto res = tu.assignment(tu.mul(tu.load(rs1+ traits::X0, 0),tu.load(rs2+ traits::X0, 0)),64);
auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.load(rs1+ traits::X0, 0),64,true),tu.ext(tu.load(rs2+ traits::X0, 0),64,true))),64,true),64);
if(rd!=0) {
tu.store(rd + traits::X0,tu.ext((tu.lshr(res,tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,true));
}
@@ -2353,8 +2352,8 @@ private:
pc=pc+ 2;
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
auto load_address = tu.assignment(tu.ext((tu.add(tu.load(rs1+ 8+ traits::X0, 0),tu.constant(uimm,8))),32,true),32);
tu.store(rd+ 8 + traits::X0,tu.ext(tu.ext(tu.read_mem(traits::MEM, load_address, 32),32,false),32,true));
auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1+ 8+ traits::X0, 0),tu.constant(uimm,8))),32,true),32);
tu.store(rd+ 8 + traits::X0,tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,false),32,true));
auto returnValue = std::make_tuple(CONT);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,58);
@@ -2380,8 +2379,8 @@ private:
pc=pc+ 2;
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
auto load_address = tu.assignment(tu.ext((tu.add(tu.load(rs1+ 8+ traits::X0, 0),tu.constant(uimm,8))),32,true),32);
tu.write_mem(traits::MEM, load_address, tu.ext(tu.load(rs2+ 8+ traits::X0, 0),32,true));
auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1+ 8+ traits::X0, 0),tu.constant(uimm,8))),32,true),32);
tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+ 8+ traits::X0, 0),32,true));
auto returnValue = std::make_tuple(CONT);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,59);
@@ -2898,8 +2897,7 @@ private:
}
else{
auto offs = tu.assignment(tu.ext((tu.add(tu.load(2+ traits::X0, 0),tu.constant(uimm,8))),32,true),32);
auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,false),32);
tu.store(rd + traits::X0,tu.ext(res,32,true));
tu.store(rd + traits::X0,tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,false),32,true));
}
auto returnValue = std::make_tuple(CONT);
tu.close_scope();
@@ -3220,5 +3218,32 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
}
} // namesapce tcc
} // namespace iss
#include <iss/factory.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
std::array<bool, 2> dummy = {
core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
auto vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
auto vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})
};
}
}
extern "C" {
bool* get_tgc_c_tcc_creators() {
return iss::dummy.data();
}
}