refine and fix TGC_C iss to becoem compliant

gen_input/templates/CORENAME.h.gtl

@@ -37,7 +37,7 @@ def nativeTypeSize(int size){
 }
 def getRegisterSizes(){
     def regs = registers.collect{nativeTypeSize(it.size)}
-    regs+=[32,32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
+    regs+=[32,32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
     return regs
 }
 def getRegisterOffsets(){
@@ -94,7 +94,9 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
         ${registers.collect{it.name}.join(', ')}, NUM_REGS,
         TRAP_STATE=NUM_REGS,
         PENDING_TRAP,
-        ICOUNT
+        ICOUNT,
+        CYCLE,
+        INSTRET
     };
 
     using reg_t = uint${addrDataWidth}_t;
@@ -175,6 +177,8 @@ protected:
         }}%>
         uint32_t trap_state = 0, pending_trap = 0;
         uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
         uint32_t last_branch;
     } reg;
 #pragma pack(pop)