Back-ported DVCon turorial changes
This commit is contained in:
@ -1,9 +1,34 @@
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/*
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* BLDC.h
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/*******************************************************************************
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* Copyright (C) 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Created on: 26.06.2018
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* Author: eyck
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*/
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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||||
* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#ifndef BLDC_H_
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#define BLDC_H_
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@ -11,43 +36,47 @@
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#include <boost/numeric/odeint.hpp>
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namespace odeint = boost::numeric::odeint;
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inline
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double norm_angle(double alpha){
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double alpha_n = fmod(alpha, M_PI * 2);
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if (alpha_n < 0.) alpha_n += (M_PI * 2);
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return alpha_n;
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inline double norm_angle(double alpha) {
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double alpha_n = fmod(alpha, M_PI * 2);
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while (alpha_n < 0.) alpha_n += (M_PI * 2);
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return alpha_n;
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}
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class BLDC {
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public:
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struct Config {
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double inertia = 0.0005; /* aka 'J' in kg/(m^2) */
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double damping = 0.000089; /* aka 'B' in Nm/(rad/s) */
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double static_friction = 0.0; /* in Nm */
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//double Kv = 0.0042; /* motor constant in RPM/V */
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double Ke = 0.0042; /* back emf constant in V/rad/s*/
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double L = 0.0027; /* Coil inductance in H */
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double M = -0.000069; /* Mutual coil inductance in H */
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double R = 2.875; /* Coil resistence in Ohm */
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int NbPoles = 2; /* NbPoles / 2 = Number of pole pairs (you count the permanent magnets on the rotor to get NbPoles) */
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double inertia = 0.0005; /* aka 'J' in kg/(m^2) */
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double damping = 0.000089; /* aka 'B' in Nm/(rad/s) */
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double static_friction = 0.0; /* in Nm */
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// double Kv = 0.0042; /* motor constant in RPM/V */
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double Ke = 0.0042; /* back emf constant in V/rad/s*/
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double L = 0.0027; /* Coil inductance in H */
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double M = -0.000069; /* Mutual coil inductance in H */
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double R = 2.875; /* Coil resistence in Ohm */
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int NbPoles =
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2; /* NbPoles / 2 = Number of pole pairs (you count the permanent magnets on the rotor to get NbPoles) */
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};
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using StateVector = std::array<double, 5>;
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struct State{
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double& theta; /* angle of the rotor */
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double& omega; /* angular speed of the rotor */
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double& ia; /* phase a current */
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double& ib; /* phase b current */
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double& ic; /* phase c current */
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explicit State(StateVector& v):theta(v[0]), omega(v[1]), ia(v[2]), ib(v[3]), ic(v[4]){}
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State(State&&) = delete;
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State(const State&) = delete;
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State& operator=(const State&) = delete; // Copy assignment operator
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State& operator=(const State&&) = delete; // Move assignment operator
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~State(){}
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void init(){
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struct State {
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double θ /* angle of the rotor */
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double ω /* angular speed of the rotor */
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double &ia; /* phase a current */
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double &ib; /* phase b current */
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double ⁣ /* phase c current */
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explicit State(StateVector &v)
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: theta(v[0])
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, omega(v[1])
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, ia(v[2])
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, ib(v[3])
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, ic(v[4]) {}
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State(State &&) = delete;
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State(const State &) = delete;
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State &operator=(const State &) = delete; // Copy assignment operator
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State &operator=(const State &&) = delete; // Move assignment operator
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~State() {}
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void init() {
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theta = ia = ib = ic = 0;
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omega = 0.;
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}
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@ -57,49 +86,46 @@ public:
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virtual ~BLDC();
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void set_input(std::array<double, 3> vin){
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this->vin=vin;
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}
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void set_input(std::array<double, 3> vin) { this->vin = vin; }
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void run(double dt);
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void printToStream(std::ostream&) const;
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void printToStream(std::ostream &) const;
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double get_current_time(){return current_time;}
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double get_current_time() { return current_time; }
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std::tuple<double, double, double> get_voltages(){
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return std::tuple<double, double, double>(
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voltages[VA]+voltages[EA]+state.ia*config.R,
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voltages[VB]+voltages[EB]+state.ib*config.R,
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voltages[VC]+voltages[EC]+state.ic*config.R
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);
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std::array<double, 7> get_voltages() {
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return std::array<double, 7>{voltages[VA], voltages[VB], voltages[VC], voltages[VCENTER],
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voltages[EA], voltages[EB], voltages[EC]};
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}
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const State& getState(){ return state;}
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const State &getState() { return state; }
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void setLoad(double torque) { torque_load = torque; }
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const double dt = 0.00000001;
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void setLoad(double torque){torque_load=torque;}
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protected:
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Config config;
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StateVector stateVector;
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State state;
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std::array<double, 3> vin;
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double current_time = 0.0;
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double torque_load=0.0;
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double etorque=0.0, mtorque=0.0;
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const double dt = 0.000001;
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double torque_load = 0.0001;
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double etorque = 0.0, mtorque = 0.0;
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std::array<double, 7> voltages;
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enum VoltageNames {EA=0, EB=1, EC=2, VA=3, VB=4, VC=5, VCENTER=6};
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double calc_bemf_factor(const State& state, double theta );
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void calc_back_emf(const State& state, double theta_e );
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enum VoltageNames { EA = 0, EB = 1, EC = 2, VA = 3, VB = 4, VC = 5, VCENTER = 6 };
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double calc_bemf_factor(const State &state, double theta);
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void calc_back_emf(const State &state, double theta_e);
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void calc_voltages();
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// ODE part
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//boost::numeric::odeint::runge_kutta4< StateVector > stepper;
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//boost::numeric::odeint::runge_kutta_cash_karp54<StateVector > stepper;
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//using stepper_type = odeint::runge_kutta_dopri5<StateVector>;
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//using stepper_type = odeint::runge_kutta_cash_karp54< StateVector>;
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using stepper_type = odeint::runge_kutta_fehlberg78< StateVector>;
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void rotor_dyn( const StateVector& x , StateVector& dxdt , const double t );
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// boost::numeric::odeint::runge_kutta4< StateVector > stepper;
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// boost::numeric::odeint::runge_kutta_cash_karp54<StateVector > stepper;
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// using stepper_type = odeint::runge_kutta_dopri5<StateVector>;
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// using stepper_type = odeint::runge_kutta_cash_karp54< StateVector>;
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using stepper_type = odeint::runge_kutta_fehlberg78<StateVector>;
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void rotor_dyn(const StateVector &x, StateVector &dxdt, const double t);
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};
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std::ostream& operator<<(std::ostream& os, const BLDC& bldc);
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std::ostream &operator<<(std::ostream &os, const BLDC &bldc);
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#endif /* BLDC_H_ */
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@ -1,36 +1,66 @@
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/*
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* dcmotor.h
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/*******************************************************************************
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* Copyright (C) 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Created on: 25.07.2018
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* Author: eyck
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*/
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#ifndef _SYSC_TOP_DCMOTOR_H_
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#define _SYSC_TOP_DCMOTOR_H_
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#include "BLDC.h"
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#include "cci_configuration"
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#include "scc/traceable.h"
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#include <systemc>
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namespace sysc {
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class dc_motor: public sc_core::sc_module, public scc::traceable {
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class dc_motor : public sc_core::sc_module, public scc::traceable {
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public:
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SC_HAS_PROCESS(dc_motor);
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SC_HAS_PROCESS(dc_motor);// NOLINT
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sc_core::sc_in<double> va_i, vb_i, vc_i;
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sc_core::sc_out<double> va_o, vb_o, vc_o;
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sc_core::sc_out<double> va_o, vb_o, vc_o, vcenter_o;
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dc_motor(const sc_core::sc_module_name& nm );
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dc_motor(const sc_core::sc_module_name &nm);
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virtual ~dc_motor();
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void trace(sc_core::sc_trace_file *trf) override;
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void trace(sc_core::sc_trace_file *trf) const override;
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cci::cci_param<sc_core::sc_time> max_integ_step;
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cci::cci_param<double> load;
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private:
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void thread(void);
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BLDC bldc_model;
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const BLDC::State& bldc_state;
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const BLDC::State &bldc_state;
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std::array<double, 7> vout;
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};
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} /* namespace sysc */
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@ -1,9 +1,34 @@
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/*
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* h_bridge.h
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/*******************************************************************************
|
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* Copyright (C) 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Created on: 25.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
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#ifndef RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_
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#define RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_
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@ -13,9 +38,9 @@
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namespace sysc {
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class h_bridge: public sc_core::sc_module {
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class h_bridge : public sc_core::sc_module {
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public:
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SC_HAS_PROCESS(h_bridge);
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SC_HAS_PROCESS(h_bridge);// NOLINT
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sc_core::sc_in<sc_dt::sc_logic> ha_i, la_i;
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sc_core::sc_in<sc_dt::sc_logic> hb_i, lb_i;
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@ -25,13 +50,15 @@ public:
|
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|
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cci::cci_param<double> vcc;
|
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|
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h_bridge(const sc_core::sc_module_name& nm);
|
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h_bridge(const sc_core::sc_module_name &nm);
|
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|
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virtual ~h_bridge();
|
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|
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private:
|
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void ain_cb();
|
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void bin_cb();
|
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void cin_cb();
|
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void write_output(sc_dt::sc_logic h_i, sc_dt::sc_logic l_i, sc_core::sc_out<double> &v_o);
|
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};
|
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|
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} /* namespace sysc */
|
||||
|
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68
platform/incl/sysc/top/hifive1.h
Normal file
68
platform/incl/sysc/top/hifive1.h
Normal file
@ -0,0 +1,68 @@
|
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/*******************************************************************************
|
||||
* Copyright (C) 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _SIFIVE_HIFIVE1_H_
|
||||
#define _SIFIVE_HIFIVE1_H_
|
||||
|
||||
#include <sysc/top/terminal.h>
|
||||
#include <sysc/top/mcp_adc.h>
|
||||
#include "tlm/tlm_signal_sockets.h"
|
||||
#include <boost/preprocessor.hpp>
|
||||
#include <systemc>
|
||||
#include <sysc/SiFive/fe310.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
struct hifive1 : public sc_core::sc_module {
|
||||
|
||||
SC_HAS_PROCESS(hifive1);
|
||||
|
||||
sc_core::sc_in<bool> erst_n;
|
||||
sc_core::sc_in<double> vref_i;
|
||||
#define PORT_DECL(z, n, _) sc_core::sc_in<double> adc_ch##n##_i;
|
||||
BOOST_PP_REPEAT(8, PORT_DECL, _);
|
||||
#undef PORT_DECL
|
||||
sc_core::sc_out<sc_dt::sc_logic> ha_o, la_o, hb_o, lb_o,hc_o, lc_o;
|
||||
|
||||
hifive1(sc_core::sc_module_name nm);
|
||||
|
||||
protected:
|
||||
sc_core::sc_vector<tlm::tlm_signal<sc_dt::sc_logic>> s_gpio;
|
||||
sc_core::sc_vector<scc::tlm_signal_logic_in> h_bridge;
|
||||
fe310 i_fe310;
|
||||
terminal i_terminal;
|
||||
mcp_3208 i_adc;
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif /* _SYSC_SIFIVE_HIFIVE1_H_ */
|
||||
@ -1,47 +0,0 @@
|
||||
/*
|
||||
* mcp3008.h
|
||||
*
|
||||
* Created on: 17.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef _SYSC_TOP_MCP3008_H_
|
||||
#define _SYSC_TOP_MCP3008_H_
|
||||
|
||||
#include "scc/signal_target_mixin.h"
|
||||
#include "scc/signal_initiator_mixin.h"
|
||||
#include "sysc/tlm_extensions.h"
|
||||
#include <tlm/tlm_signal.h>
|
||||
#include "cci_configuration"
|
||||
#include <sysc/utils/sc_vector.h>
|
||||
#include <sysc/kernel/sc_module.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class mcp3008: public sc_core::sc_module {
|
||||
public:
|
||||
SC_HAS_PROCESS(mcp3008);
|
||||
scc::tlm_signal_logic_in sck_i;
|
||||
scc::tlm_signal_logic_out miso_o;
|
||||
scc::tlm_signal_logic_in mosi_i;
|
||||
scc::tlm_signal_logic_in cs_i;
|
||||
|
||||
sc_core::sc_in<double> vref_i;
|
||||
sc_core::sc_vector<sc_core::sc_in<double>> ch_i;
|
||||
|
||||
mcp3008(sc_core::sc_module_name nm);
|
||||
virtual ~mcp3008();
|
||||
|
||||
private:
|
||||
tlm::tlm_sync_enum receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
|
||||
void do_conversion();
|
||||
unsigned idx, rx_bits;
|
||||
std::array<uint8_t, 3> rx_bytes, tx_bytes;
|
||||
sc_dt::sc_logic mosi_v, miso_v, cs_v;
|
||||
sysc::tlm_signal_spi_extension* ext, tx_ext;
|
||||
sc_core::sc_time last_tx_start;
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _SYSC_TOP_MCP3008_H_ */
|
||||
120
platform/incl/sysc/top/mcp_adc.h
Normal file
120
platform/incl/sysc/top/mcp_adc.h
Normal file
@ -0,0 +1,120 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _SYSC_TOP_MCP3008_H_
|
||||
#define _SYSC_TOP_MCP3008_H_
|
||||
|
||||
#include "cci_configuration"
|
||||
#include "scc/signal_initiator_mixin.h"
|
||||
#include "scc/signal_target_mixin.h"
|
||||
#include "sysc/tlm_extensions.h"
|
||||
#include <sysc/kernel/sc_module.h>
|
||||
#include <sysc/utils/sc_vector.h>
|
||||
#include <tlm/tlm_signal.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class mcp_adc : public sc_core::sc_module {
|
||||
public:
|
||||
|
||||
template <typename TYPE>
|
||||
static std::unique_ptr<mcp_adc> create(sc_core::sc_module_name nm);
|
||||
|
||||
scc::tlm_signal_logic_in sck_i;
|
||||
scc::tlm_signal_logic_out miso_o;
|
||||
scc::tlm_signal_logic_in mosi_i;
|
||||
scc::tlm_signal_logic_in cs_i;
|
||||
|
||||
sc_core::sc_in<double> vref_i;
|
||||
sc_core::sc_vector<sc_core::sc_in<double>> ch_i;
|
||||
|
||||
mcp_adc(mcp_adc &other) = delete;
|
||||
|
||||
mcp_adc(mcp_adc &&other) = delete;
|
||||
|
||||
mcp_adc &operator=(mcp_adc &other) = delete;
|
||||
|
||||
mcp_adc &operator=(mcp_adc &&other) = delete;
|
||||
|
||||
~mcp_adc() override = default;
|
||||
|
||||
protected:
|
||||
mcp_adc(sc_core::sc_module_name nm, size_t channel_no)
|
||||
: sc_core::sc_module(nm)
|
||||
, NAMED(sck_i)
|
||||
, NAMED(miso_o)
|
||||
, NAMED(mosi_i)
|
||||
, NAMED(cs_i)
|
||||
, NAMED(vref_i)
|
||||
, NAMED(ch_i, channel_no) {}
|
||||
};
|
||||
|
||||
class mcp_3008 : public mcp_adc {
|
||||
public:
|
||||
SC_HAS_PROCESS(mcp_3008);// NOLINT
|
||||
|
||||
mcp_3008(sc_core::sc_module_name nm);
|
||||
~mcp_3008() override = default;
|
||||
|
||||
private:
|
||||
tlm::tlm_sync_enum receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
|
||||
void do_conversion();
|
||||
unsigned idx, rx_bits;
|
||||
std::array<uint8_t, 3> rx_bytes, tx_bytes;
|
||||
sc_dt::sc_logic mosi_v, miso_v, cs_v;
|
||||
sysc::tlm_signal_spi_extension *ext, tx_ext;
|
||||
sc_core::sc_time last_tx_start;
|
||||
};
|
||||
|
||||
class mcp_3208 : public mcp_adc {
|
||||
public:
|
||||
SC_HAS_PROCESS(mcp_3208);// NOLINT
|
||||
|
||||
mcp_3208(sc_core::sc_module_name nm);
|
||||
~mcp_3208() override = default;
|
||||
|
||||
private:
|
||||
tlm::tlm_sync_enum receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
|
||||
void sample_inputs();
|
||||
void do_conversion();
|
||||
unsigned idx, rx_bits, byte_offs, bit_offs;
|
||||
std::array<uint8_t, 3> rx_bytes, tx_bytes;
|
||||
sc_dt::sc_logic mosi_v, sck_v, cs_v;
|
||||
sysc::tlm_signal_spi_extension *ext, tx_ext;
|
||||
sc_core::sc_time last_tx_start;
|
||||
sc_core::sc_event clk_sample_evt;
|
||||
};
|
||||
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _SYSC_TOP_MCP3008_H_ */
|
||||
@ -1,42 +1,62 @@
|
||||
/*
|
||||
* system.h
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Created on: 11.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __SYSC_GENERAL_SYSTEM_H_
|
||||
#define __SYSC_GENERAL_SYSTEM_H_
|
||||
|
||||
#include <systemc>
|
||||
#include "sysc/SiFive/hifive1.h"
|
||||
#include "mcp3008.h"
|
||||
#include "terminal.h"
|
||||
#include "h_bridge.h"
|
||||
#include "dcmotor.h"
|
||||
#include "h_bridge.h"
|
||||
#include <memory>
|
||||
#include <systemc>
|
||||
#include "hifive1.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class system: sc_core::sc_module {
|
||||
class system : sc_core::sc_module {
|
||||
public:
|
||||
SC_HAS_PROCESS(system);
|
||||
SC_HAS_PROCESS(system);// NOLINT
|
||||
|
||||
system(sc_core::sc_module_name nm);
|
||||
virtual ~system();
|
||||
|
||||
|
||||
private:
|
||||
sc_core::sc_vector<tlm::tlm_signal<sc_dt::sc_logic>> s_gpio;
|
||||
sc_core::sc_signal<sc_dt::sc_logic> s_ha, s_la, s_hb, s_lb, s_hc, s_lc;
|
||||
sc_core::sc_signal<bool> s_rst_n;
|
||||
sc_core::sc_signal<double> s_vref, s_va, s_vb, s_vc, s_vasens, s_vbsens, s_vcsens;
|
||||
sc_core::sc_signal<double> s_vref, s_va, s_vb, s_vc, s_vasens, s_vbsens, s_vcsens, s_vcentersens;
|
||||
sc_core::sc_vector<sc_core::sc_signal<double>> s_ana;
|
||||
sysc::hifive1 i_platform;
|
||||
sysc::terminal i_terminal;
|
||||
sysc::mcp3008 i_adc;
|
||||
sysc::hifive1 i_hifive1;
|
||||
sysc::h_bridge i_h_bridge;
|
||||
sysc::dc_motor i_motor;
|
||||
void gen_por();
|
||||
};
|
||||
|
||||
}
|
||||
#endif /* __SYSC_GENERAL_SYSTEM_H_ */
|
||||
|
||||
@ -1,31 +1,56 @@
|
||||
/*
|
||||
* terminal.h
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Created on: 07.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _SYSC_TOP_TERMINAL_H_
|
||||
#define _SYSC_TOP_TERMINAL_H_
|
||||
|
||||
#include "scc/signal_target_mixin.h"
|
||||
#include "scc/signal_initiator_mixin.h"
|
||||
#include "tlm/tlm_signal.h"
|
||||
#include "cci_configuration"
|
||||
#include <sysc/kernel/sc_module.h>
|
||||
#include "scc/signal_initiator_mixin.h"
|
||||
#include "scc/signal_target_mixin.h"
|
||||
#include "tlm/tlm_signal.h"
|
||||
#include <memory>
|
||||
#include <sysc/kernel/sc_module.h>
|
||||
|
||||
namespace sysc {
|
||||
class WsHandler;
|
||||
|
||||
class terminal: public sc_core::sc_module {
|
||||
class terminal : public sc_core::sc_module {
|
||||
public:
|
||||
scc::tlm_signal_logic_out tx_o;
|
||||
scc::tlm_signal_logic_in rx_i;
|
||||
scc::tlm_signal_logic_in rx_i;
|
||||
|
||||
terminal();
|
||||
|
||||
terminal(const sc_core::sc_module_name& nm);
|
||||
terminal(const sc_core::sc_module_name &nm);
|
||||
|
||||
virtual ~terminal();
|
||||
|
||||
@ -33,11 +58,11 @@ public:
|
||||
|
||||
protected:
|
||||
void before_end_of_elaboration();
|
||||
void receive(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, sc_core::sc_time& delay);
|
||||
void receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay);
|
||||
|
||||
std::vector<uint8_t> queue;
|
||||
std::shared_ptr<sysc::WsHandler> handler;
|
||||
sc_core::sc_time last_tx_start=sc_core::SC_ZERO_TIME;
|
||||
sc_core::sc_time last_tx_start = sc_core::SC_ZERO_TIME;
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user