DBT-RISE/DBT-RISE-TGC
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fixes wrong mcounteren in M-mode only priv wrapper

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Eyck Jentzsch
2022-10-10 08:59:27 +02:00
parent 40d1966e9a
commit 1a0fc4bd5d
1 changed files with 0 additions and 2 deletions
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src/iss/arch/riscv_hart_m_p.h
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@@ -408,8 +408,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
csr_rd_cb[mie] = &this_class::read_ie; csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie; csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid; csr_rd_cb[mhartid] = &this_class::read_hartid;
csr_rd_cb[mcounteren] = &this_class::read_null;
csr_wr_cb[mcounteren] = &this_class::write_null;
csr_wr_cb[misa] = &this_class::write_null; csr_wr_cb[misa] = &this_class::write_null;
csr_wr_cb[mvendorid] = &this_class::write_null; csr_wr_cb[mvendorid] = &this_class::write_null;
csr_wr_cb[marchid] = &this_class::write_null; csr_wr_cb[marchid] = &this_class::write_null;