Adapted descriptions to improved Core DSL and regenerated code

riscv/gen_input/minres_rv.core_desc

@@ -8,7 +8,6 @@ import "RV64IBase.core_desc"
 //import "RV64M.core_desc"
 import "RV64A.core_desc"
 
-
 Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
     template:"vm_riscv.in.cpp";
     constants {
@@ -17,8 +16,8 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
         // definitions for the architecture wrapper
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         MISA_VAL:=0b01000000000101000001000100000101;
-        PGSIZE := 4096; //1 << 12;
-        PGMASK := 4095; //PGSIZE-1
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
     }
 }
 
@@ -30,8 +29,8 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
         // definitions for the architecture wrapper
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         MISA_VAL:=0b01000000000101000001000100101101;
-        PGSIZE := 4096; //1 << 12;
-        PGMASK := 4095; //PGSIZE-1
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
     }
 }
 
@@ -44,7 +43,7 @@ Core RV64IA provides RV64IBase, RV64A, RV32A {
         // definitions for the architecture wrapper
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         MISA_VAL:=0b10000000000001000000000100000001;
-        PGSIZE := 4096; //1 << 12;
-        PGMASK := 4095; //PGSIZE-1
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
     }
 }