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add support for non-compressed ISA

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Eyck Jentzsch
2021-09-23 21:09:36 +02:00
parent ba9339a50d
commit 174259155d
3 changed files with 107 additions and 3 deletions
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11
incl/iss/arch/riscv_hart_m_p.h
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@ -920,7 +920,16 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
if (trap_id == 0) { // exception
// store ret addr in xepc register
csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
switch(cause){
case 0:
csr[mtval] = instr;
break;
case 2:
csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
break;
default:
csr[mtval] = fault_data;
}
fault_data = 0;
} else {
csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt