add support for non-compressed ISA

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -64,7 +64,9 @@ public:
     using addr_t      = typename super::addr_t;
     using reg_t       = typename traits::reg_t;
     using mem_type_e  = typename traits::mem_type_e;
-
+    
+    const bool has_compressed = traits::MISA_VAL & 0b100;
+    
     vm_impl();
 
     vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
@@ -210,6 +212,7 @@ private:
         <%instr.behavior.eachLine{%>${it}
         <%}%>} catch(...){}
         // post execution stuff
+        if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0,  0);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
         // trap check
         if(*trap_state!=0){
@@ -324,6 +327,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             if (is_jump_to_self_enabled(cond) &&
                     (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
             auto f = decode_inst(insn);
+            auto old_pc = pc.val;
             pc = (this->*f)(pc, insn);
         }
     }