regenerated sources and and add opcode enum to headers

gen_input/CoreDSL-Instruction-Set-Description

@@ -1 +1 @@
-Subproject commit 5f78c1fd8965170d418afc55605a94dc0ef4dd75
+Subproject commit 3cfac1d86f6532140a04cdfc1501f1b8f3729632

gen_input/templates/interp/CORENAME.h.gtl

@@ -46,6 +46,13 @@ def getRegisterOffsets(){
     }
     return regs
 }
+def byteSize(int size){
+    if(size<=8) return 8;
+    if(size<=16) return 16;
+    if(size<=32) return 32;
+    if(size<=64) return 64;
+    return 128;
+}
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
@@ -107,6 +114,11 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
     enum sreg_flag_e { FLAGS };
 
     enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    
+    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
+        ${instr.instruction.name} = ${index},<%}%>
+        MAX_OPCODE
+    };
 };
 
 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -154,9 +166,9 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 protected:
     struct ${coreDef.name}_regs {<%
         registers.each { reg -> if(reg.size>0) {%> 
-        uint${reg.size}_t ${reg.name} = 0;<%
+        uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
         }}%>
-        uint${pc.size}_t NEXT_${pc.name} = 0;
+        uint${byteSize(pc.size)}_t NEXT_${pc.name} = 0;
         uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
         uint64_t icount = 0;
     } reg;

incl/iss/arch/tgf_b.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,6 @@
  *
  *******************************************************************************/
 
-
 #ifndef _TGF_B_H_
 #define _TGF_B_H_
 
@@ -48,13 +47,13 @@ template <> struct traits<tgf_b> {
 
     constexpr static char const* const core_type = "TGF_B";
     
-  	static constexpr std::array<const char*, 33> reg_names{
+    static constexpr std::array<const char*, 35> reg_names{
- 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
  
-  	static constexpr std::array<const char*, 33> reg_aliases{
+    static constexpr std::array<const char*, 35> reg_aliases{
- 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
 
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
@@ -92,45 +91,14 @@ template <> struct traits<tgf_b> {
         X30,
         X31,
         PC,
+        PRIV,
         NUM_REGS,
         NEXT_PC=NUM_REGS,
         TRAP_STATE,
         PENDING_TRAP,
         MACHINE_STATE,
         LAST_BRANCH,
-        ICOUNT,
+        ICOUNT
-        ZERO = X0,
-        RA = X1,
-        SP = X2,
-        GP = X3,
-        TP = X4,
-        T0 = X5,
-        T1 = X6,
-        T2 = X7,
-        S0 = X8,
-        S1 = X9,
-        A0 = X10,
-        A1 = X11,
-        A2 = X12,
-        A3 = X13,
-        A4 = X14,
-        A5 = X15,
-        A6 = X16,
-        A7 = X17,
-        S2 = X18,
-        S3 = X19,
-        S4 = X20,
-        S5 = X21,
-        S6 = X22,
-        S7 = X23,
-        S8 = X24,
-        S9 = X25,
-        S10 = X26,
-        S11 = X27,
-        T3 = X28,
-        T4 = X29,
-        T5 = X30,
-        T6 = X31
     };
 
     using reg_t = uint32_t;
@@ -143,17 +111,73 @@ template <> struct traits<tgf_b> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
- 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
+    static constexpr std::array<const uint32_t, 40> reg_bit_widths{
- 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,2,32,32,32,32,32,64}};
 
     static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,133,137,141,145,149,153}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
     enum mem_type_e { MEM, CSR, FENCE, RES };
+    
+    enum class opcode_e : unsigned short {
+        LUI = 0,
+        AUIPC = 1,
+        JAL = 2,
+        JALR = 3,
+        BEQ = 4,
+        BNE = 5,
+        BLT = 6,
+        BGE = 7,
+        BLTU = 8,
+        BGEU = 9,
+        LB = 10,
+        LH = 11,
+        LW = 12,
+        LBU = 13,
+        LHU = 14,
+        SB = 15,
+        SH = 16,
+        SW = 17,
+        ADDI = 18,
+        SLTI = 19,
+        SLTIU = 20,
+        XORI = 21,
+        ORI = 22,
+        ANDI = 23,
+        SLLI = 24,
+        SRLI = 25,
+        SRAI = 26,
+        ADD = 27,
+        SUB = 28,
+        SLL = 29,
+        SLT = 30,
+        SLTU = 31,
+        XOR = 32,
+        SRL = 33,
+        SRA = 34,
+        OR = 35,
+        AND = 36,
+        FENCE = 37,
+        FENCE_I = 38,
+        ECALL = 39,
+        EBREAK = 40,
+        URET = 41,
+        SRET = 42,
+        MRET = 43,
+        WFI = 44,
+        SFENCE_VMA = 45,
+        CSRRW = 46,
+        CSRRS = 47,
+        CSRRC = 48,
+        CSRRWI = 49,
+        CSRRSI = 50,
+        CSRRCI = 51,
+        MAX_OPCODE
+    };
 };
 
 struct tgf_b: public arch_if {
@@ -233,6 +257,7 @@ protected:
         uint32_t X30 = 0; 
         uint32_t X31 = 0; 
         uint32_t PC = 0; 
+        uint8_t PRIV = 0;
         uint32_t NEXT_PC = 0;
         uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
         uint64_t icount = 0;

incl/iss/arch/tgf_c.h

@@ -122,6 +122,98 @@ template <> struct traits<tgf_c> {
     enum sreg_flag_e { FLAGS };
 
     enum mem_type_e { MEM, CSR, FENCE, RES };
+    
+    enum class opcode_e : unsigned short {
+        LUI = 0,
+        AUIPC = 1,
+        JAL = 2,
+        JALR = 3,
+        BEQ = 4,
+        BNE = 5,
+        BLT = 6,
+        BGE = 7,
+        BLTU = 8,
+        BGEU = 9,
+        LB = 10,
+        LH = 11,
+        LW = 12,
+        LBU = 13,
+        LHU = 14,
+        SB = 15,
+        SH = 16,
+        SW = 17,
+        ADDI = 18,
+        SLTI = 19,
+        SLTIU = 20,
+        XORI = 21,
+        ORI = 22,
+        ANDI = 23,
+        SLLI = 24,
+        SRLI = 25,
+        SRAI = 26,
+        ADD = 27,
+        SUB = 28,
+        SLL = 29,
+        SLT = 30,
+        SLTU = 31,
+        XOR = 32,
+        SRL = 33,
+        SRA = 34,
+        OR = 35,
+        AND = 36,
+        FENCE = 37,
+        FENCE_I = 38,
+        ECALL = 39,
+        EBREAK = 40,
+        URET = 41,
+        SRET = 42,
+        MRET = 43,
+        WFI = 44,
+        SFENCE_VMA = 45,
+        CSRRW = 46,
+        CSRRS = 47,
+        CSRRC = 48,
+        CSRRWI = 49,
+        CSRRSI = 50,
+        CSRRCI = 51,
+        MUL = 52,
+        MULH = 53,
+        MULHSU = 54,
+        MULHU = 55,
+        DIV = 56,
+        DIVU = 57,
+        REM = 58,
+        REMU = 59,
+        CADDI4SPN = 60,
+        CLW = 61,
+        CSW = 62,
+        CADDI = 63,
+        CNOP = 64,
+        CJAL = 65,
+        CLI = 66,
+        CLUI = 67,
+        CADDI16SP = 68,
+        CSRLI = 69,
+        CSRAI = 70,
+        CANDI = 71,
+        CSUB = 72,
+        CXOR = 73,
+        COR = 74,
+        CAND = 75,
+        CJ = 76,
+        CBEQZ = 77,
+        CBNEZ = 78,
+        CSLLI = 79,
+        CLWSP = 80,
+        CMV = 81,
+        CJR = 82,
+        CADD = 83,
+        CJALR = 84,
+        CEBREAK = 85,
+        CSWSP = 86,
+        DII = 87,
+        MAX_OPCODE
+    };
 };
 
 struct tgf_c: public arch_if {

src/iss/tgf_b.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -39,9 +39,9 @@
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_names;
+constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgf_b>::reg_names;
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
+constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
 constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
 
 tgf_b::tgf_b() {

src/vm/interp/vm_tgf_c.cpp

@@ -516,7 +516,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+rs1) == *(X+rs2)? *PC + imm : *PC + 4;
+        if(*(X+rs1) == *(X+rs2)) *PC = *PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
@@ -550,7 +550,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+rs1) != *(X+rs2)? *PC + imm : *PC + 4;
+        if(*(X+rs1) != *(X+rs2)) *PC = *PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
@@ -584,7 +584,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+rs1) < *(X+rs2)? *PC + imm : *PC + 4;
+        if(*(X+rs1) < *(X+rs2)) *PC = *PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
@@ -618,7 +618,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+rs1) >= *(X+rs2)? *PC + imm : *PC + 4;
+        if(*(X+rs1) >= *(X+rs2)) *PC = *PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
@@ -652,7 +652,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+rs1) < *(X+rs2)? *PC + imm : *PC + 4;
+        if(*(X+rs1) < *(X+rs2)) *PC = *PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
@@ -686,7 +686,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+rs1) >= *(X+rs2)? *PC + imm : *PC + 4;
+        if(*(X+rs1) >= *(X+rs2)) *PC = *PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);
@@ -788,7 +788,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        if(rd != 0) *(X+rd) = (int32_t)readSpace4(traits::MEM, *(X+rs1) + imm); 
+        if(rd != 0) *(X+rd) = (uint32_t)readSpace4(traits::MEM, *(X+rs1) + imm); 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 12);
@@ -3076,7 +3076,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+(rs1 + 8)) == 0? (int8_t)*PC + imm : *PC + 2;
+        if(*(X+(rs1 + 8)) == 0) *PC = (int8_t)*PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
@@ -3109,7 +3109,7 @@ private:
         uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
         uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
         // execute instruction
-        *PC = *(X+(rs1 + 8)) != 0? (int8_t)*PC + imm : *PC + 2;
+        if(*(X+(rs1 + 8)) != 0) *PC = (int8_t)*PC + imm; 
         // post execution stuff
         super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);