DBT-RISE/DBT-RISE-TGC
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regenerated sources and and add opcode enum to headers

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This commit is contained in:
Eyck Jentzsch
2021-02-23 08:29:12 +00:00
parent d8e009c72b
commit 1668df0531
7 changed files with 960 additions and 759 deletions
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64
gen_input/templates/interp/CORENAME.h.gtl
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@ -31,21 +31,28 @@
*******************************************************************************/
<%
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=pc.size // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
def regs = registers.collect{it.size}
regs[-1]=pc.size // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
return regs
}
def getRegisterOffsets(){
def regs = registers.collect{it.offset}
def offs= regs[-1]
// append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT offsets starting with NEXT_PC size
[pc.size/8, 4, 4, 4, 4].each{ sz ->
regs+=offs+sz
offs+=sz
}
def regs = registers.collect{it.offset}
def offs= regs[-1]
// append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT offsets starting with NEXT_PC size
[pc.size/8, 4, 4, 4, 4].each{ sz ->
regs+=offs+sz
offs+=sz
}
return regs
}
def byteSize(int size){
if(size<=8) return 8;
if(size<=16) return 16;
if(size<=32) return 32;
if(size<=64) return 64;
return 128;
}
%>
#ifndef _${coreDef.name.toUpperCase()}_H_
#define _${coreDef.name.toUpperCase()}_H_
@ -62,20 +69,20 @@ struct ${coreDef.name.toLowerCase()};
template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${registers.size}> reg_names{
{"${registers.collect{it.name}.join('", "')}"}};
static constexpr std::array<const char*, ${registers.size}> reg_names{
{"${registers.collect{it.name}.join('", "')}"}};
static constexpr std::array<const char*, ${registers.size}> reg_aliases{
{"${registers.collect{it.alias}.join('", "')}"}};
static constexpr std::array<const char*, ${registers.size}> reg_aliases{
{"${registers.collect{it.alias}.join('", "')}"}};
enum constants {${constants.collect{c -> c.name+"="+c.value}.join(', ')}};
constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e {<%
registers.each { reg -> %>
registers.each { reg -> %>
${reg.name},<%
}%>
NEXT_${pc.name}=NUM_REGS,
@ -96,17 +103,22 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
{${getRegisterSizes().join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
{${getRegisterSizes().join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
{${getRegisterOffsets().join(',')}}};
{${getRegisterOffsets().join(',')}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
${instr.instruction.name} = ${index},<%}%>
MAX_OPCODE
};
};
struct ${coreDef.name.toLowerCase()}: public arch_if {
@ -153,10 +165,10 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
protected:
struct ${coreDef.name}_regs {<%
registers.each { reg -> if(reg.size>0) {%>
uint${reg.size}_t ${reg.name} = 0;<%
registers.each { reg -> if(reg.size>0) {%>
uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
}}%>
uint${pc.size}_t NEXT_${pc.name} = 0;
uint${byteSize(pc.size)}_t NEXT_${pc.name} = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
@ -167,11 +179,11 @@ protected:
<%
def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}
uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}
<%} else { %>
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
<%}%>
};