[WIP] started to add TinyCC backend
This commit is contained in:
@@ -0,0 +1,514 @@
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial API and implementation
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////////////////////////////////////////////////////////////////////////////////
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#include <iss/iss.h>
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#include <iss/llvm/vm_base.h>
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extern "C" {
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#include <softfloat.h>
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#include "internals.h"
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#include "specialize.h"
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}
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#include <limits>
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namespace iss {
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namespace vm {
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namespace fp_impl {
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using namespace std;
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#define INT_TYPE(L) Type::getIntNTy(mod->getContext(), L)
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#define FLOAT_TYPE Type::getFloatTy(mod->getContext())
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#define DOUBLE_TYPE Type::getDoubleTy(mod->getContext())
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#define VOID_TYPE Type::getVoidTy(mod->getContext())
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#define THIS_PTR_TYPE Type::getIntNPtrTy(mod->getContext(), 8)
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#define FDECLL(NAME, RET, ...) \
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Function *NAME##_func = CurrentModule->getFunction(#NAME); \
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if (!NAME##_func) { \
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std::vector<Type *> NAME##_args{__VA_ARGS__}; \
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FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false); \
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NAME##_func = Function::Create(NAME##_type, GlobalValue::ExternalLinkage, #NAME, CurrentModule); \
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NAME##_func->setCallingConv(CallingConv::C); \
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}
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#define FDECL(NAME, RET, ...) \
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std::vector<Type *> NAME##_args{__VA_ARGS__}; \
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FunctionType *NAME##_type = llvm::FunctionType::get(RET, NAME##_args, false); \
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mod->getOrInsertFunction(#NAME, NAME##_type);
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using namespace llvm;
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void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
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if(flen){
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FDECL(fget_flags, INT_TYPE(32));
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FDECL(fadd_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fsub_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fmul_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fdiv_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fsqrt_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fcmp_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
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FDECL(fcvt_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fmadd_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fsel_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
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FDECL(fclass_s, INT_TYPE(32), INT_TYPE(32));
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FDECL(fcvt_32_64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
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FDECL(fcvt_64_32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
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if(flen>32){
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FDECL(fconv_d2f, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
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FDECL(fconv_f2d, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
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FDECL(fadd_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
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FDECL(fsub_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
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FDECL(fmul_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
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FDECL(fdiv_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
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FDECL(fsqrt_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
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FDECL(fcmp_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
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FDECL(fcvt_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
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FDECL(fmadd_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
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FDECL(fsel_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
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FDECL(fclass_d, INT_TYPE(64), INT_TYPE(64));
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FDECL(unbox_s, INT_TYPE(32), INT_TYPE(64));
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}
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}
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}
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}
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}
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}
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using this_t = uint8_t *;
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const uint8_t rmm_map[] = {
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softfloat_round_near_even /*RNE*/,
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softfloat_round_minMag/*RTZ*/,
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softfloat_round_min/*RDN*/,
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softfloat_round_max/*RUP?*/,
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softfloat_round_near_maxMag /*RMM*/,
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softfloat_round_max/*RTZ*/,
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softfloat_round_max/*RTZ*/,
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softfloat_round_max/*RTZ*/,
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};
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const uint32_t quiet_nan32=0x7fC00000;
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extern "C" {
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uint32_t fget_flags(){
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return softfloat_exceptionFlags&0x1f;
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}
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uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r =f32_add(v1f, v2f);
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return r.v;
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}
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uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_sub(v1f, v2f);
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return r.v;
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}
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uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_mul(v1f, v2f);
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return r.v;
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}
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uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_div(v1f, v2f);
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return r.v;
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}
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uint32_t fsqrt_s(uint32_t v1, uint8_t mode) {
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float32_t v1f{v1};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_sqrt(v1f);
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return r.v;
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}
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uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
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float32_t v1f{v1},v2f{v2};
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softfloat_exceptionFlags=0;
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bool nan = (v1&defaultNaNF32UI)==quiet_nan32 || (v2&defaultNaNF32UI)==quiet_nan32;
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bool snan = softfloat_isSigNaNF32UI(v1) || softfloat_isSigNaNF32UI(v2);
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switch(op){
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case 0:
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if(nan | snan){
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if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f32_eq(v1f,v2f )?1:0;
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case 1:
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if(nan | snan){
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softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f32_le(v1f,v2f )?1:0;
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case 2:
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if(nan | snan){
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softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f32_lt(v1f,v2f )?1:0;
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default:
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break;
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}
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return -1;
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}
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uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
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float32_t v1f{v1};
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softfloat_exceptionFlags=0;
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float32_t r;
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switch(op){
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case 0:{ //w->s, fp to int32
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uint_fast32_t res = f32_to_i32(v1f,rmm_map[mode&0x7],true);
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return (uint32_t)res;
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}
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case 1:{ //wu->s
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uint_fast32_t res = f32_to_ui32(v1f,rmm_map[mode&0x7],true);
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return (uint32_t)res;
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}
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case 2: //s->w
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r=i32_to_f32(v1);
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return r.v;
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case 3: //s->wu
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r=ui32_to_f32(v1);
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return r.v;
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}
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return 0;
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}
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uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode) {
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// op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t res = softfloat_mulAddF32(v1, v2, v3, op&0x1);
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if(op>1) res.v ^= 1ULL<<31;
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return res.v;
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}
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uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) {
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softfloat_exceptionFlags = 0;
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bool v1_nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI;
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bool v2_nan = (v2 & defaultNaNF32UI) == defaultNaNF32UI;
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bool v1_snan = softfloat_isSigNaNF32UI(v1);
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bool v2_snan = softfloat_isSigNaNF32UI(v2);
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if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
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if (v1_nan || v1_snan)
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return (v2_nan || v2_snan) ? defaultNaNF32UI : v2;
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else
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if (v2_nan || v2_snan)
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return v1;
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else {
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if ((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
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return op == 0 ? ((v1 & 0x80000000) ? v1 : v2) : ((v1 & 0x80000000) ? v2 : v1);
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} else {
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float32_t v1f{ v1 }, v2f{ v2 };
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return op == 0 ? (f32_lt(v1f, v2f) ? v1 : v2) : (f32_lt(v1f, v2f) ? v2 : v1);
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}
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}
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}
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uint32_t fclass_s( uint32_t v1 ){
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float32_t a{v1};
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union ui32_f32 uA;
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uint_fast32_t uiA;
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uA.f = a;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF;
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uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0;
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bool sign = signF32UI( uiA );
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bool fracZero = fracF32UI( uiA ) == 0;
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bool isNaN = isNaNF32UI( uiA );
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bool isSNaN = softfloat_isSigNaNF32UI( uiA );
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return
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( sign && infOrNaN && fracZero ) << 0 |
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( sign && !infOrNaN && !subnormalOrZero ) << 1 |
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( sign && subnormalOrZero && !fracZero ) << 2 |
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( sign && subnormalOrZero && fracZero ) << 3 |
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( !sign && infOrNaN && fracZero ) << 7 |
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( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
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( !sign && subnormalOrZero && !fracZero ) << 5 |
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( !sign && subnormalOrZero && fracZero ) << 4 |
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( isNaN && isSNaN ) << 8 |
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( isNaN && !isSNaN ) << 9;
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}
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uint32_t fconv_d2f(uint64_t v1, uint8_t mode){
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softfloat_roundingMode=rmm_map[mode&0x7];
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bool nan = (v1 & defaultNaNF64UI)==defaultNaNF64UI;
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if(nan){
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return defaultNaNF32UI;
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} else {
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float32_t res = f64_to_f32(float64_t{v1});
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return res.v;
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}
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}
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uint64_t fconv_f2d(uint32_t v1, uint8_t mode){
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bool nan = (v1 & defaultNaNF32UI)==defaultNaNF32UI;
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if(nan){
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return defaultNaNF64UI;
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} else {
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softfloat_roundingMode=rmm_map[mode&0x7];
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float64_t res = f32_to_f64(float32_t{v1});
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return res.v;
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}
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}
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uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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bool nan = (v1&defaultNaNF32UI)==quiet_nan32;
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bool snan = softfloat_isSigNaNF32UI(v1);
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float64_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float64_t r =f64_add(v1f, v2f);
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return r.v;
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}
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uint64_t fsub_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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float64_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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||||
float64_t r=f64_sub(v1f, v2f);
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return r.v;
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}
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uint64_t fmul_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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float64_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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||||
softfloat_exceptionFlags=0;
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||||
float64_t r=f64_mul(v1f, v2f);
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return r.v;
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||||
}
|
||||
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||||
uint64_t fdiv_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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||||
float64_t v1f{v1},v2f{v2};
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||||
softfloat_roundingMode=rmm_map[mode&0x7];
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||||
softfloat_exceptionFlags=0;
|
||||
float64_t r=f64_div(v1f, v2f);
|
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return r.v;
|
||||
}
|
||||
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||||
uint64_t fsqrt_d(uint64_t v1, uint8_t mode) {
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float64_t v1f{v1};
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softfloat_roundingMode=rmm_map[mode&0x7];
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||||
softfloat_exceptionFlags=0;
|
||||
float64_t r=f64_sqrt(v1f);
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return r.v;
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||||
}
|
||||
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||||
uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
|
||||
float64_t v1f{v1},v2f{v2};
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||||
softfloat_exceptionFlags=0;
|
||||
bool nan = (v1&defaultNaNF64UI)==quiet_nan32 || (v2&defaultNaNF64UI)==quiet_nan32;
|
||||
bool snan = softfloat_isSigNaNF64UI(v1) || softfloat_isSigNaNF64UI(v2);
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||||
switch(op){
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||||
case 0:
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||||
if(nan | snan){
|
||||
if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
|
||||
return 0;
|
||||
} else
|
||||
return f64_eq(v1f,v2f )?1:0;
|
||||
case 1:
|
||||
if(nan | snan){
|
||||
softfloat_raiseFlags(softfloat_flag_invalid);
|
||||
return 0;
|
||||
} else
|
||||
return f64_le(v1f,v2f )?1:0;
|
||||
case 2:
|
||||
if(nan | snan){
|
||||
softfloat_raiseFlags(softfloat_flag_invalid);
|
||||
return 0;
|
||||
} else
|
||||
return f64_lt(v1f,v2f )?1:0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
|
||||
float64_t v1f{v1};
|
||||
softfloat_exceptionFlags=0;
|
||||
float64_t r;
|
||||
switch(op){
|
||||
case 0:{ //l->d, fp to int32
|
||||
int64_t res = f64_to_i64(v1f,rmm_map[mode&0x7],true);
|
||||
return (uint64_t)res;
|
||||
}
|
||||
case 1:{ //lu->s
|
||||
uint64_t res = f64_to_ui64(v1f,rmm_map[mode&0x7],true);
|
||||
return res;
|
||||
}
|
||||
case 2: //s->l
|
||||
r=i64_to_f64(v1);
|
||||
return r.v;
|
||||
case 3: //s->lu
|
||||
r=ui64_to_f64(v1);
|
||||
return r.v;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
|
||||
// op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
|
||||
softfloat_roundingMode=rmm_map[mode&0x7];
|
||||
softfloat_exceptionFlags=0;
|
||||
float64_t res = softfloat_mulAddF64(v1, v2, v3, op&0x1);
|
||||
if(op>1) res.v ^= 1ULL<<63;
|
||||
return res.v;
|
||||
}
|
||||
|
||||
uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) {
|
||||
softfloat_exceptionFlags = 0;
|
||||
bool v1_nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI;
|
||||
bool v2_nan = (v2 & defaultNaNF64UI) == defaultNaNF64UI;
|
||||
bool v1_snan = softfloat_isSigNaNF64UI(v1);
|
||||
bool v2_snan = softfloat_isSigNaNF64UI(v2);
|
||||
if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
|
||||
if (v1_nan || v1_snan)
|
||||
return (v2_nan || v2_snan) ? defaultNaNF64UI : v2;
|
||||
else
|
||||
if (v2_nan || v2_snan)
|
||||
return v1;
|
||||
else {
|
||||
if ((v1 & std::numeric_limits<int64_t>::max()) == 0 && (v2 & std::numeric_limits<int64_t>::max()) == 0) {
|
||||
return op == 0 ?
|
||||
((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2) :
|
||||
((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
|
||||
} else {
|
||||
float64_t v1f{ v1 }, v2f{ v2 };
|
||||
return op == 0 ?
|
||||
(f64_lt(v1f, v2f) ? v1 : v2) :
|
||||
(f64_lt(v1f, v2f) ? v2 : v1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t fclass_d(uint64_t v1 ){
|
||||
|
||||
float64_t a{v1};
|
||||
union ui64_f64 uA;
|
||||
uint_fast64_t uiA;
|
||||
|
||||
uA.f = a;
|
||||
uiA = uA.ui;
|
||||
|
||||
uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF;
|
||||
uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0;
|
||||
bool sign = signF64UI( uiA );
|
||||
bool fracZero = fracF64UI( uiA ) == 0;
|
||||
bool isNaN = isNaNF64UI( uiA );
|
||||
bool isSNaN = softfloat_isSigNaNF64UI( uiA );
|
||||
|
||||
return
|
||||
( sign && infOrNaN && fracZero ) << 0 |
|
||||
( sign && !infOrNaN && !subnormalOrZero ) << 1 |
|
||||
( sign && subnormalOrZero && !fracZero ) << 2 |
|
||||
( sign && subnormalOrZero && fracZero ) << 3 |
|
||||
( !sign && infOrNaN && fracZero ) << 7 |
|
||||
( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
|
||||
( !sign && subnormalOrZero && !fracZero ) << 5 |
|
||||
( !sign && subnormalOrZero && fracZero ) << 4 |
|
||||
( isNaN && isSNaN ) << 8 |
|
||||
( isNaN && !isSNaN ) << 9;
|
||||
}
|
||||
|
||||
uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode) {
|
||||
float32_t v1f{v1};
|
||||
softfloat_exceptionFlags=0;
|
||||
float64_t r;
|
||||
switch(op){
|
||||
case 0: //l->s, fp to int32
|
||||
return f32_to_i64(v1f,rmm_map[mode&0x7],true);
|
||||
case 1: //wu->s
|
||||
return f32_to_ui64(v1f,rmm_map[mode&0x7],true);
|
||||
case 2: //s->w
|
||||
r=i32_to_f64(v1);
|
||||
return r.v;
|
||||
case 3: //s->wu
|
||||
r=ui32_to_f64(v1);
|
||||
return r.v;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t fcvt_64_32(uint64_t v1, uint32_t op, uint8_t mode) {
|
||||
softfloat_exceptionFlags=0;
|
||||
float32_t r;
|
||||
switch(op){
|
||||
case 0:{ //wu->s
|
||||
int32_t r=f64_to_i32(float64_t{v1}, rmm_map[mode&0x7],true);
|
||||
return r;
|
||||
}
|
||||
case 1:{ //wu->s
|
||||
uint32_t r=f64_to_ui32(float64_t{v1}, rmm_map[mode&0x7],true);
|
||||
return r;
|
||||
}
|
||||
case 2: //l->s, fp to int32
|
||||
r=i64_to_f32(v1);
|
||||
return r.v;
|
||||
case 3: //wu->s
|
||||
r=ui64_to_f32(v1);
|
||||
return r.v;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t unbox_s(uint64_t v){
|
||||
constexpr uint64_t mask = std::numeric_limits<uint64_t>::max() & ~((uint64_t)std::numeric_limits<uint32_t>::max());
|
||||
if((v & mask) != mask)
|
||||
return 0x7fc00000;
|
||||
else
|
||||
return v & std::numeric_limits<uint32_t>::max();
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,610 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/mnrv32.h>
|
||||
#include <iss/arch/riscv_hart_msu_vp.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/tcc/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
#include <sstream>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
#include <fmt/format.h>
|
||||
|
||||
#include <array>
|
||||
#include <iss/debugger/riscv_target_adapter.h>
|
||||
|
||||
namespace iss {
|
||||
namespace tcc {
|
||||
namespace mnrv32 {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
using namespace iss::vm::tcc;
|
||||
|
||||
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
|
||||
public:
|
||||
using super = typename iss::vm::tcc::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
|
||||
using Value = void;
|
||||
using ConstantInt = void;
|
||||
using Type = void;
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
|
||||
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
||||
|
||||
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
||||
debugger_if::dbg_enabled = true;
|
||||
if (vm_base<ARCH>::tgt_adapter == nullptr)
|
||||
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
||||
return vm_base<ARCH>::tgt_adapter;
|
||||
}
|
||||
|
||||
protected:
|
||||
using vm_base<ARCH>::get_reg_ptr;
|
||||
|
||||
using this_class = vm_impl<ARCH>;
|
||||
using compile_ret_t = std::tuple<continuation_e>;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, std::ostringstream&);
|
||||
|
||||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
template <typename T> inline ConstantInt *size(T type) {
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
void setup_module(Module* m) override {
|
||||
super::setup_module(m);
|
||||
}
|
||||
|
||||
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
|
||||
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
|
||||
}
|
||||
|
||||
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, std::ostringstream&) override;
|
||||
|
||||
void gen_leave_behavior(std::ostringstream& os) override;
|
||||
|
||||
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
|
||||
|
||||
void gen_leave_trap(unsigned lvl);
|
||||
|
||||
void gen_wait(unsigned type);
|
||||
|
||||
void gen_trap_behavior(std::ostringstream& os) override;
|
||||
|
||||
void gen_trap_check(std::ostringstream& os){}
|
||||
|
||||
inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
|
||||
return this->builder.CreateLoad(get_reg_ptr(i), false);
|
||||
}
|
||||
|
||||
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
|
||||
Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
|
||||
this->get_type(traits<ARCH>::XLEN));
|
||||
this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
|
||||
}
|
||||
|
||||
// some compile time constants
|
||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
||||
|
||||
std::array<compile_func, LUT_SIZE> lut;
|
||||
|
||||
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||
std::array<compile_func, LUT_SIZE> lut_11;
|
||||
|
||||
std::array<compile_func *, 4> qlut;
|
||||
|
||||
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
|
||||
|
||||
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
|
||||
compile_func f) {
|
||||
if (pos < 0) {
|
||||
lut[idx] = f;
|
||||
} else {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
|
||||
} else {
|
||||
if ((valid & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
|
||||
} else {
|
||||
auto new_val = idx << 1;
|
||||
if ((value & bitmask) != 0) new_val++;
|
||||
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
|
||||
|
||||
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
|
||||
if (pos >= 0) {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
lut_val = extract_fields(pos - 1, val, mask, lut_val);
|
||||
} else {
|
||||
auto new_val = lut_val << 1;
|
||||
if ((val & bitmask) != 0) new_val++;
|
||||
lut_val = extract_fields(pos - 1, val, mask, new_val);
|
||||
}
|
||||
}
|
||||
return lut_val;
|
||||
}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct InstructionDesriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
compile_func op;
|
||||
};
|
||||
|
||||
const std::array<InstructionDesriptor, 52> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */
|
||||
/* instruction LUI */
|
||||
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
|
||||
/* instruction AUIPC */
|
||||
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
|
||||
/* instruction JAL */
|
||||
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
|
||||
/* instruction JALR */
|
||||
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
|
||||
/* instruction BEQ */
|
||||
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
|
||||
/* instruction BNE */
|
||||
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
|
||||
/* instruction BLT */
|
||||
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
|
||||
/* instruction BGE */
|
||||
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
|
||||
/* instruction BLTU */
|
||||
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
|
||||
/* instruction BGEU */
|
||||
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
|
||||
/* instruction LB */
|
||||
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
|
||||
/* instruction LH */
|
||||
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
|
||||
/* instruction LW */
|
||||
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
|
||||
/* instruction LBU */
|
||||
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
|
||||
/* instruction LHU */
|
||||
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
|
||||
/* instruction SB */
|
||||
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
|
||||
/* instruction SH */
|
||||
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
|
||||
/* instruction SW */
|
||||
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
|
||||
/* instruction ADDI */
|
||||
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
|
||||
/* instruction SLTI */
|
||||
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
|
||||
/* instruction SLTIU */
|
||||
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
|
||||
/* instruction XORI */
|
||||
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
|
||||
/* instruction ORI */
|
||||
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
|
||||
/* instruction ANDI */
|
||||
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
|
||||
/* instruction SLLI */
|
||||
{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
|
||||
/* instruction SRLI */
|
||||
{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
|
||||
/* instruction SRAI */
|
||||
{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
|
||||
/* instruction ADD */
|
||||
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
|
||||
/* instruction SUB */
|
||||
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
|
||||
/* instruction SLL */
|
||||
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
|
||||
/* instruction SLT */
|
||||
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
|
||||
/* instruction SLTU */
|
||||
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
|
||||
/* instruction XOR */
|
||||
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
|
||||
/* instruction SRL */
|
||||
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
|
||||
/* instruction SRA */
|
||||
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
|
||||
/* instruction OR */
|
||||
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
|
||||
/* instruction AND */
|
||||
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
|
||||
/* instruction FENCE */
|
||||
{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
|
||||
/* instruction FENCE_I */
|
||||
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
|
||||
/* instruction ECALL */
|
||||
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
|
||||
/* instruction EBREAK */
|
||||
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
|
||||
/* instruction URET */
|
||||
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
|
||||
/* instruction SRET */
|
||||
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
|
||||
/* instruction MRET */
|
||||
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
|
||||
/* instruction WFI */
|
||||
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
|
||||
/* instruction SFENCE.VMA */
|
||||
{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
|
||||
/* instruction CSRRW */
|
||||
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
|
||||
/* instruction CSRRS */
|
||||
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
|
||||
/* instruction CSRRC */
|
||||
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
|
||||
/* instruction CSRRWI */
|
||||
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
|
||||
/* instruction CSRRSI */
|
||||
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
|
||||
/* instruction CSRRCI */
|
||||
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
|
||||
}};
|
||||
|
||||
/* instruction definitions */
|
||||
/* instruction 0: LUI */
|
||||
compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 1: AUIPC */
|
||||
compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 2: JAL */
|
||||
compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
this->gen_sync(PRE_SYNC, 0);
|
||||
|
||||
uint8_t rd = ((bit_sub<7,5>(instr)));
|
||||
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
||||
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
|
||||
if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
auto mnemonic = fmt::format(
|
||||
"{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
|
||||
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
||||
os<<"print_disass(0x"<<std::hex<<this->core_ptr<<", 0x"<<pc.val<<", \""<<mnemonic<<"\");\n";
|
||||
}
|
||||
|
||||
auto cur_pc_val = pc.val;
|
||||
pc=pc+4;
|
||||
}
|
||||
|
||||
/* instruction 3: JALR */
|
||||
compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 4: BEQ */
|
||||
compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 5: BNE */
|
||||
compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 6: BLT */
|
||||
compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 7: BGE */
|
||||
compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 8: BLTU */
|
||||
compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 9: BGEU */
|
||||
compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 10: LB */
|
||||
compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 11: LH */
|
||||
compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 12: LW */
|
||||
compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 13: LBU */
|
||||
compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 14: LHU */
|
||||
compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 15: SB */
|
||||
compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 16: SH */
|
||||
compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 17: SW */
|
||||
compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 18: ADDI */
|
||||
compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 19: SLTI */
|
||||
compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 20: SLTIU */
|
||||
compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 21: XORI */
|
||||
compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 22: ORI */
|
||||
compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 23: ANDI */
|
||||
compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 24: SLLI */
|
||||
compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 25: SRLI */
|
||||
compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 26: SRAI */
|
||||
compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 27: ADD */
|
||||
compile_ret_t __add(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 28: SUB */
|
||||
compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 29: SLL */
|
||||
compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 30: SLT */
|
||||
compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 31: SLTU */
|
||||
compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 32: XOR */
|
||||
compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 33: SRL */
|
||||
compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 34: SRA */
|
||||
compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 35: OR */
|
||||
compile_ret_t __or(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 36: AND */
|
||||
compile_ret_t __and(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 37: FENCE */
|
||||
compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 38: FENCE_I */
|
||||
compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 39: ECALL */
|
||||
compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 40: EBREAK */
|
||||
compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 41: URET */
|
||||
compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 42: SRET */
|
||||
compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 43: MRET */
|
||||
compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 44: WFI */
|
||||
compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 45: SFENCE.VMA */
|
||||
compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 46: CSRRW */
|
||||
compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 47: CSRRS */
|
||||
compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 48: CSRRC */
|
||||
compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 49: CSRRWI */
|
||||
compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 50: CSRRSI */
|
||||
compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 51: CSRRCI */
|
||||
compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* end opcode definitions
|
||||
****************************************************************************/
|
||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, std::ostringstream& oss) {
|
||||
vm_impl::gen_sync(iss::PRE_SYNC, instr_descr.size());
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
gen_raise_trap(0, 2); // illegal instruction trap
|
||||
vm_impl::gen_sync(iss::POST_SYNC, instr_descr.size());
|
||||
vm_impl::gen_trap_check(oss);
|
||||
return BRANCH;
|
||||
}
|
||||
};
|
||||
|
||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||
volatile CODE_WORD x = insn;
|
||||
insn = 2 * x;
|
||||
}
|
||||
|
||||
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||
|
||||
template <typename ARCH>
|
||||
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||
: vm_base<ARCH>(core, core_id, cluster_id) {
|
||||
qlut[0] = lut_00.data();
|
||||
qlut[1] = lut_01.data();
|
||||
qlut[2] = lut_10.data();
|
||||
qlut[3] = lut_11.data();
|
||||
for (auto instr : instr_descr) {
|
||||
auto quantrant = instr.value & 0x3;
|
||||
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
||||
}
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
std::tuple<continuation_e>
|
||||
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, std::ostringstream& os) {
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
code_word_t insn = 0;
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
phys_addr_t paddr(pc);
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
paddr = this->core.v2p(pc);
|
||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
auto res = this->core.read(paddr, 2, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||
}
|
||||
} else {
|
||||
auto res = this->core.read(paddr, 4, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
}
|
||||
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
// curr pc on stack
|
||||
++inst_cnt;
|
||||
auto lut_val = extract_fields(insn);
|
||||
auto f = qlut[insn & 0x3][lut_val];
|
||||
if (f == nullptr) {
|
||||
f = &this_class::illegal_intruction;
|
||||
}
|
||||
return (this->*f)(pc, insn, os);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(std::ostringstream& os) {
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(std::ostringstream& os) {
|
||||
}
|
||||
|
||||
} // namespace mnrv32
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::mnrv32>(arch::mnrv32 *core, unsigned short port, bool dump) {
|
||||
auto ret = new mnrv32::vm_impl<arch::mnrv32>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
}
|
||||
} // namespace iss
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,913 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/rv32imac.h>
|
||||
#include <iss/arch/riscv_hart_msu_vp.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/llvm/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
#include <fmt/format.h>
|
||||
|
||||
#include <array>
|
||||
#include <iss/debugger/riscv_target_adapter.h>
|
||||
|
||||
namespace iss {
|
||||
namespace vm {
|
||||
namespace fp_impl {
|
||||
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
|
||||
}
|
||||
}
|
||||
|
||||
namespace tcc {
|
||||
namespace rv32imac {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
using namespace iss::vm::llvm;
|
||||
|
||||
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
|
||||
public:
|
||||
using super = typename iss::vm::llvm::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
|
||||
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
||||
|
||||
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
||||
debugger_if::dbg_enabled = true;
|
||||
if (vm_base<ARCH>::tgt_adapter == nullptr)
|
||||
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
||||
return vm_base<ARCH>::tgt_adapter;
|
||||
}
|
||||
|
||||
protected:
|
||||
using vm_base<ARCH>::get_reg_ptr;
|
||||
|
||||
using this_class = vm_impl<ARCH>;
|
||||
using compile_ret_t = std::tuple<continuation_e>;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, std::ostringstream&);
|
||||
|
||||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
template <typename T> inline ConstantInt *size(T type) {
|
||||
return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
|
||||
}
|
||||
|
||||
void setup_module(Module* m) override {
|
||||
super::setup_module(m);
|
||||
iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
|
||||
}
|
||||
|
||||
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
|
||||
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
|
||||
}
|
||||
|
||||
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, std::ostringstream&) override;
|
||||
|
||||
void gen_leave_behavior(BasicBlock *leave_blk) override;
|
||||
|
||||
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
|
||||
|
||||
void gen_leave_trap(unsigned lvl);
|
||||
|
||||
void gen_wait(unsigned type);
|
||||
|
||||
void gen_trap_behavior(BasicBlock *) override;
|
||||
|
||||
void gen_trap_check(BasicBlock *bb);
|
||||
|
||||
inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
|
||||
return this->builder.CreateLoad(get_reg_ptr(i), false);
|
||||
}
|
||||
|
||||
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
|
||||
Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
|
||||
this->get_type(traits<ARCH>::XLEN));
|
||||
this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
|
||||
}
|
||||
|
||||
// some compile time constants
|
||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
||||
|
||||
std::array<compile_func, LUT_SIZE> lut;
|
||||
|
||||
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||
std::array<compile_func, LUT_SIZE> lut_11;
|
||||
|
||||
std::array<compile_func *, 4> qlut;
|
||||
|
||||
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
|
||||
|
||||
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
|
||||
compile_func f) {
|
||||
if (pos < 0) {
|
||||
lut[idx] = f;
|
||||
} else {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
|
||||
} else {
|
||||
if ((valid & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
|
||||
} else {
|
||||
auto new_val = idx << 1;
|
||||
if ((value & bitmask) != 0) new_val++;
|
||||
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
|
||||
|
||||
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
|
||||
if (pos >= 0) {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
lut_val = extract_fields(pos - 1, val, mask, lut_val);
|
||||
} else {
|
||||
auto new_val = lut_val << 1;
|
||||
if ((val & bitmask) != 0) new_val++;
|
||||
lut_val = extract_fields(pos - 1, val, mask, new_val);
|
||||
}
|
||||
}
|
||||
return lut_val;
|
||||
}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct InstructionDesriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
compile_func op;
|
||||
};
|
||||
|
||||
const std::array<InstructionDesriptor, 99> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */
|
||||
/* instruction JALR */
|
||||
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
|
||||
/* instruction C.ADDI4SPN */
|
||||
{16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn},
|
||||
/* instruction C.LW */
|
||||
{16, 0b0100000000000000, 0b1110000000000011, &this_class::__c_lw},
|
||||
/* instruction C.SW */
|
||||
{16, 0b1100000000000000, 0b1110000000000011, &this_class::__c_sw},
|
||||
/* instruction C.ADDI */
|
||||
{16, 0b0000000000000001, 0b1110000000000011, &this_class::__c_addi},
|
||||
/* instruction C.NOP */
|
||||
{16, 0b0000000000000001, 0b1111111111111111, &this_class::__c_nop},
|
||||
/* instruction C.JAL */
|
||||
{16, 0b0010000000000001, 0b1110000000000011, &this_class::__c_jal},
|
||||
/* instruction C.LI */
|
||||
{16, 0b0100000000000001, 0b1110000000000011, &this_class::__c_li},
|
||||
/* instruction C.LUI */
|
||||
{16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui},
|
||||
/* instruction C.ADDI16SP */
|
||||
{16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp},
|
||||
/* instruction C.SRLI */
|
||||
{16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli},
|
||||
/* instruction C.SRAI */
|
||||
{16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai},
|
||||
/* instruction C.ANDI */
|
||||
{16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi},
|
||||
/* instruction C.SUB */
|
||||
{16, 0b1000110000000001, 0b1111110001100011, &this_class::__c_sub},
|
||||
/* instruction C.XOR */
|
||||
{16, 0b1000110000100001, 0b1111110001100011, &this_class::__c_xor},
|
||||
/* instruction C.OR */
|
||||
{16, 0b1000110001000001, 0b1111110001100011, &this_class::__c_or},
|
||||
/* instruction C.AND */
|
||||
{16, 0b1000110001100001, 0b1111110001100011, &this_class::__c_and},
|
||||
/* instruction C.J */
|
||||
{16, 0b1010000000000001, 0b1110000000000011, &this_class::__c_j},
|
||||
/* instruction C.BEQZ */
|
||||
{16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz},
|
||||
/* instruction C.BNEZ */
|
||||
{16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez},
|
||||
/* instruction C.SLLI */
|
||||
{16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli},
|
||||
/* instruction C.LWSP */
|
||||
{16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp},
|
||||
/* instruction C.MV */
|
||||
{16, 0b1000000000000010, 0b1111000000000011, &this_class::__c_mv},
|
||||
/* instruction C.JR */
|
||||
{16, 0b1000000000000010, 0b1111000001111111, &this_class::__c_jr},
|
||||
/* instruction C.ADD */
|
||||
{16, 0b1001000000000010, 0b1111000000000011, &this_class::__c_add},
|
||||
/* instruction C.JALR */
|
||||
{16, 0b1001000000000010, 0b1111000001111111, &this_class::__c_jalr},
|
||||
/* instruction C.EBREAK */
|
||||
{16, 0b1001000000000010, 0b1111111111111111, &this_class::__c_ebreak},
|
||||
/* instruction C.SWSP */
|
||||
{16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp},
|
||||
/* instruction DII */
|
||||
{16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
|
||||
/* instruction LR.W */
|
||||
{32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lr_w},
|
||||
/* instruction SC.W */
|
||||
{32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__sc_w},
|
||||
/* instruction AMOSWAP.W */
|
||||
{32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_w},
|
||||
/* instruction AMOADD.W */
|
||||
{32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_w},
|
||||
/* instruction AMOXOR.W */
|
||||
{32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_w},
|
||||
/* instruction AMOAND.W */
|
||||
{32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_w},
|
||||
/* instruction AMOOR.W */
|
||||
{32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_w},
|
||||
/* instruction AMOMIN.W */
|
||||
{32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_w},
|
||||
/* instruction AMOMAX.W */
|
||||
{32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_w},
|
||||
/* instruction AMOMINU.W */
|
||||
{32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w},
|
||||
/* instruction AMOMAXU.W */
|
||||
{32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w},
|
||||
/* instruction MUL */
|
||||
{32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul},
|
||||
/* instruction MULH */
|
||||
{32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh},
|
||||
/* instruction MULHSU */
|
||||
{32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu},
|
||||
/* instruction MULHU */
|
||||
{32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu},
|
||||
/* instruction DIV */
|
||||
{32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div},
|
||||
/* instruction DIVU */
|
||||
{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu},
|
||||
/* instruction REM */
|
||||
{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
|
||||
/* instruction REMU */
|
||||
{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
|
||||
/* instruction LUI */
|
||||
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
|
||||
/* instruction AUIPC */
|
||||
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
|
||||
/* instruction JAL */
|
||||
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
|
||||
/* instruction BEQ */
|
||||
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
|
||||
/* instruction BNE */
|
||||
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
|
||||
/* instruction BLT */
|
||||
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
|
||||
/* instruction BGE */
|
||||
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
|
||||
/* instruction BLTU */
|
||||
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
|
||||
/* instruction BGEU */
|
||||
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
|
||||
/* instruction LB */
|
||||
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
|
||||
/* instruction LH */
|
||||
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
|
||||
/* instruction LW */
|
||||
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
|
||||
/* instruction LBU */
|
||||
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
|
||||
/* instruction LHU */
|
||||
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
|
||||
/* instruction SB */
|
||||
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
|
||||
/* instruction SH */
|
||||
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
|
||||
/* instruction SW */
|
||||
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
|
||||
/* instruction ADDI */
|
||||
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
|
||||
/* instruction SLTI */
|
||||
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
|
||||
/* instruction SLTIU */
|
||||
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
|
||||
/* instruction XORI */
|
||||
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
|
||||
/* instruction ORI */
|
||||
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
|
||||
/* instruction ANDI */
|
||||
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
|
||||
/* instruction SLLI */
|
||||
{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
|
||||
/* instruction SRLI */
|
||||
{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
|
||||
/* instruction SRAI */
|
||||
{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
|
||||
/* instruction ADD */
|
||||
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
|
||||
/* instruction SUB */
|
||||
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
|
||||
/* instruction SLL */
|
||||
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
|
||||
/* instruction SLT */
|
||||
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
|
||||
/* instruction SLTU */
|
||||
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
|
||||
/* instruction XOR */
|
||||
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
|
||||
/* instruction SRL */
|
||||
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
|
||||
/* instruction SRA */
|
||||
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
|
||||
/* instruction OR */
|
||||
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
|
||||
/* instruction AND */
|
||||
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
|
||||
/* instruction FENCE */
|
||||
{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
|
||||
/* instruction FENCE_I */
|
||||
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
|
||||
/* instruction ECALL */
|
||||
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
|
||||
/* instruction EBREAK */
|
||||
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
|
||||
/* instruction URET */
|
||||
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
|
||||
/* instruction SRET */
|
||||
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
|
||||
/* instruction MRET */
|
||||
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
|
||||
/* instruction WFI */
|
||||
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
|
||||
/* instruction SFENCE.VMA */
|
||||
{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
|
||||
/* instruction CSRRW */
|
||||
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
|
||||
/* instruction CSRRS */
|
||||
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
|
||||
/* instruction CSRRC */
|
||||
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
|
||||
/* instruction CSRRWI */
|
||||
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
|
||||
/* instruction CSRRSI */
|
||||
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
|
||||
/* instruction CSRRCI */
|
||||
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
|
||||
}};
|
||||
|
||||
/* instruction definitions */
|
||||
/* instruction 0: JALR */
|
||||
compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 1: C.ADDI4SPN */
|
||||
compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 2: C.LW */
|
||||
compile_ret_t __c_lw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 3: C.SW */
|
||||
compile_ret_t __c_sw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 4: C.ADDI */
|
||||
compile_ret_t __c_addi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 5: C.NOP */
|
||||
compile_ret_t __c_nop(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 6: C.JAL */
|
||||
compile_ret_t __c_jal(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 7: C.LI */
|
||||
compile_ret_t __c_li(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 8: C.LUI */
|
||||
compile_ret_t __c_lui(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 9: C.ADDI16SP */
|
||||
compile_ret_t __c_addi16sp(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 10: C.SRLI */
|
||||
compile_ret_t __c_srli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 11: C.SRAI */
|
||||
compile_ret_t __c_srai(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 12: C.ANDI */
|
||||
compile_ret_t __c_andi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 13: C.SUB */
|
||||
compile_ret_t __c_sub(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 14: C.XOR */
|
||||
compile_ret_t __c_xor(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 15: C.OR */
|
||||
compile_ret_t __c_or(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 16: C.AND */
|
||||
compile_ret_t __c_and(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 17: C.J */
|
||||
compile_ret_t __c_j(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 18: C.BEQZ */
|
||||
compile_ret_t __c_beqz(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 19: C.BNEZ */
|
||||
compile_ret_t __c_bnez(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 20: C.SLLI */
|
||||
compile_ret_t __c_slli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 21: C.LWSP */
|
||||
compile_ret_t __c_lwsp(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 22: C.MV */
|
||||
compile_ret_t __c_mv(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 23: C.JR */
|
||||
compile_ret_t __c_jr(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 24: C.ADD */
|
||||
compile_ret_t __c_add(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 25: C.JALR */
|
||||
compile_ret_t __c_jalr(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 26: C.EBREAK */
|
||||
compile_ret_t __c_ebreak(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 27: C.SWSP */
|
||||
compile_ret_t __c_swsp(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 28: DII */
|
||||
compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 29: LR.W */
|
||||
compile_ret_t __lr_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 30: SC.W */
|
||||
compile_ret_t __sc_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 31: AMOSWAP.W */
|
||||
compile_ret_t __amoswap_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 32: AMOADD.W */
|
||||
compile_ret_t __amoadd_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 33: AMOXOR.W */
|
||||
compile_ret_t __amoxor_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 34: AMOAND.W */
|
||||
compile_ret_t __amoand_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 35: AMOOR.W */
|
||||
compile_ret_t __amoor_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 36: AMOMIN.W */
|
||||
compile_ret_t __amomin_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 37: AMOMAX.W */
|
||||
compile_ret_t __amomax_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 38: AMOMINU.W */
|
||||
compile_ret_t __amominu_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 39: AMOMAXU.W */
|
||||
compile_ret_t __amomaxu_w(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 40: MUL */
|
||||
compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 41: MULH */
|
||||
compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 42: MULHSU */
|
||||
compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 43: MULHU */
|
||||
compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 44: DIV */
|
||||
compile_ret_t __div(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 45: DIVU */
|
||||
compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 46: REM */
|
||||
compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 47: REMU */
|
||||
compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 48: LUI */
|
||||
compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 49: AUIPC */
|
||||
compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 50: JAL */
|
||||
compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 51: BEQ */
|
||||
compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 52: BNE */
|
||||
compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 53: BLT */
|
||||
compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 54: BGE */
|
||||
compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 55: BLTU */
|
||||
compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 56: BGEU */
|
||||
compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 57: LB */
|
||||
compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 58: LH */
|
||||
compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 59: LW */
|
||||
compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 60: LBU */
|
||||
compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 61: LHU */
|
||||
compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 62: SB */
|
||||
compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 63: SH */
|
||||
compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 64: SW */
|
||||
compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 65: ADDI */
|
||||
compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 66: SLTI */
|
||||
compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 67: SLTIU */
|
||||
compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 68: XORI */
|
||||
compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 69: ORI */
|
||||
compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 70: ANDI */
|
||||
compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 71: SLLI */
|
||||
compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 72: SRLI */
|
||||
compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 73: SRAI */
|
||||
compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 74: ADD */
|
||||
compile_ret_t __add(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 75: SUB */
|
||||
compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 76: SLL */
|
||||
compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 77: SLT */
|
||||
compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 78: SLTU */
|
||||
compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 79: XOR */
|
||||
compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 80: SRL */
|
||||
compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 81: SRA */
|
||||
compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 82: OR */
|
||||
compile_ret_t __or(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 83: AND */
|
||||
compile_ret_t __and(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 84: FENCE */
|
||||
compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 85: FENCE_I */
|
||||
compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 86: ECALL */
|
||||
compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 87: EBREAK */
|
||||
compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 88: URET */
|
||||
compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 89: SRET */
|
||||
compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 90: MRET */
|
||||
compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 91: WFI */
|
||||
compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 92: SFENCE.VMA */
|
||||
compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 93: CSRRW */
|
||||
compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 94: CSRRS */
|
||||
compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 95: CSRRC */
|
||||
compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 96: CSRRWI */
|
||||
compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 97: CSRRSI */
|
||||
compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 98: CSRRCI */
|
||||
compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* end opcode definitions
|
||||
****************************************************************************/
|
||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, std::stringstream& os) {
|
||||
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
|
||||
this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
|
||||
get_reg_ptr(traits<ARCH>::PC), true);
|
||||
this->builder.CreateStore(
|
||||
this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
|
||||
this->gen_const(64U, 1)),
|
||||
get_reg_ptr(traits<ARCH>::ICOUNT), true);
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
this->gen_raise_trap(0, 2); // illegal instruction trap
|
||||
this->gen_sync(iss::POST_SYNC, instr_descr.size());
|
||||
this->gen_trap_check(this->leave_blk);
|
||||
return BRANCH;
|
||||
}
|
||||
};
|
||||
|
||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||
volatile CODE_WORD x = insn;
|
||||
insn = 2 * x;
|
||||
}
|
||||
|
||||
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||
|
||||
template <typename ARCH>
|
||||
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||
: vm_base<ARCH>(core, core_id, cluster_id) {
|
||||
qlut[0] = lut_00.data();
|
||||
qlut[1] = lut_01.data();
|
||||
qlut[2] = lut_10.data();
|
||||
qlut[3] = lut_11.data();
|
||||
for (auto instr : instr_descr) {
|
||||
auto quantrant = instr.value & 0x3;
|
||||
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
||||
}
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
std::tuple<continuation_e>
|
||||
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, std::ostringstrem& os) {
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
code_word_t insn = 0;
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
phys_addr_t paddr(pc);
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
paddr = this->core.v2p(pc);
|
||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
auto res = this->core.read(paddr, 2, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||
}
|
||||
} else {
|
||||
auto res = this->core.read(paddr, 4, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
}
|
||||
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
// curr pc on stack
|
||||
++inst_cnt;
|
||||
auto lut_val = extract_fields(insn);
|
||||
auto f = qlut[insn & 0x3][lut_val];
|
||||
if (f == nullptr) {
|
||||
f = &this_class::illegal_intruction;
|
||||
}
|
||||
return (this->*f)(pc, insn, this_block);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
|
||||
this->builder.SetInsertPoint(leave_blk);
|
||||
this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
|
||||
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
|
||||
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
|
||||
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
|
||||
this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
|
||||
auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
|
||||
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
|
||||
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
|
||||
this->builder.CreateCall(this->mod->getFunction("wait"), args);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
|
||||
this->builder.SetInsertPoint(trap_blk);
|
||||
auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
|
||||
get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
|
||||
this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
|
||||
this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
|
||||
auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||
this->builder.CreateRet(trap_addr_val);
|
||||
}
|
||||
|
||||
template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
|
||||
auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
|
||||
this->gen_cond_branch(this->builder.CreateICmp(
|
||||
ICmpInst::ICMP_EQ, v,
|
||||
ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
|
||||
bb, this->trap_blk, 1);
|
||||
}
|
||||
} // namespace rv32imac
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, unsigned short port, bool dump) {
|
||||
auto ret = new rv32imac::vm_impl<arch::rv32imac>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
}
|
||||
} // namespace iss
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,703 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/rv64i.h>
|
||||
#include <iss/arch/riscv_hart_msu_vp.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/llvm/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
#include <fmt/format.h>
|
||||
|
||||
#include <array>
|
||||
#include <iss/debugger/riscv_target_adapter.h>
|
||||
|
||||
namespace iss {
|
||||
namespace vm {
|
||||
namespace fp_impl {
|
||||
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
|
||||
}
|
||||
}
|
||||
|
||||
namespace tcc {
|
||||
namespace rv64i {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
using namespace iss::vm::llvm;
|
||||
|
||||
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
|
||||
public:
|
||||
using super = typename iss::vm::llvm::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
|
||||
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
||||
|
||||
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
||||
debugger_if::dbg_enabled = true;
|
||||
if (vm_base<ARCH>::tgt_adapter == nullptr)
|
||||
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
||||
return vm_base<ARCH>::tgt_adapter;
|
||||
}
|
||||
|
||||
protected:
|
||||
using vm_base<ARCH>::get_reg_ptr;
|
||||
|
||||
using this_class = vm_impl<ARCH>;
|
||||
using compile_ret_t = std::tuple<continuation_e>;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, std::ostringstream&);
|
||||
|
||||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
template <typename T> inline ConstantInt *size(T type) {
|
||||
return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
|
||||
}
|
||||
|
||||
void setup_module(Module* m) override {
|
||||
super::setup_module(m);
|
||||
iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
|
||||
}
|
||||
|
||||
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
|
||||
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
|
||||
}
|
||||
|
||||
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, std::ostringstream&) override;
|
||||
|
||||
void gen_leave_behavior(BasicBlock *leave_blk) override;
|
||||
|
||||
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
|
||||
|
||||
void gen_leave_trap(unsigned lvl);
|
||||
|
||||
void gen_wait(unsigned type);
|
||||
|
||||
void gen_trap_behavior(BasicBlock *) override;
|
||||
|
||||
void gen_trap_check(BasicBlock *bb);
|
||||
|
||||
inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
|
||||
return this->builder.CreateLoad(get_reg_ptr(i), false);
|
||||
}
|
||||
|
||||
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
|
||||
Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
|
||||
this->get_type(traits<ARCH>::XLEN));
|
||||
this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
|
||||
}
|
||||
|
||||
// some compile time constants
|
||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
||||
|
||||
std::array<compile_func, LUT_SIZE> lut;
|
||||
|
||||
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||
std::array<compile_func, LUT_SIZE> lut_11;
|
||||
|
||||
std::array<compile_func *, 4> qlut;
|
||||
|
||||
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
|
||||
|
||||
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
|
||||
compile_func f) {
|
||||
if (pos < 0) {
|
||||
lut[idx] = f;
|
||||
} else {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
|
||||
} else {
|
||||
if ((valid & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
|
||||
} else {
|
||||
auto new_val = idx << 1;
|
||||
if ((value & bitmask) != 0) new_val++;
|
||||
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
|
||||
|
||||
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
|
||||
if (pos >= 0) {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
lut_val = extract_fields(pos - 1, val, mask, lut_val);
|
||||
} else {
|
||||
auto new_val = lut_val << 1;
|
||||
if ((val & bitmask) != 0) new_val++;
|
||||
lut_val = extract_fields(pos - 1, val, mask, new_val);
|
||||
}
|
||||
}
|
||||
return lut_val;
|
||||
}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct InstructionDesriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
compile_func op;
|
||||
};
|
||||
|
||||
const std::array<InstructionDesriptor, 64> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */
|
||||
/* instruction LUI */
|
||||
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
|
||||
/* instruction AUIPC */
|
||||
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
|
||||
/* instruction JAL */
|
||||
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
|
||||
/* instruction JALR */
|
||||
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
|
||||
/* instruction BEQ */
|
||||
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
|
||||
/* instruction BNE */
|
||||
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
|
||||
/* instruction BLT */
|
||||
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
|
||||
/* instruction BGE */
|
||||
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
|
||||
/* instruction BLTU */
|
||||
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
|
||||
/* instruction BGEU */
|
||||
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
|
||||
/* instruction LB */
|
||||
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
|
||||
/* instruction LH */
|
||||
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
|
||||
/* instruction LW */
|
||||
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
|
||||
/* instruction LBU */
|
||||
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
|
||||
/* instruction LHU */
|
||||
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
|
||||
/* instruction SB */
|
||||
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
|
||||
/* instruction SH */
|
||||
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
|
||||
/* instruction SW */
|
||||
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
|
||||
/* instruction ADDI */
|
||||
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
|
||||
/* instruction SLTI */
|
||||
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
|
||||
/* instruction SLTIU */
|
||||
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
|
||||
/* instruction XORI */
|
||||
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
|
||||
/* instruction ORI */
|
||||
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
|
||||
/* instruction ANDI */
|
||||
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
|
||||
/* instruction SLLI */
|
||||
{32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli},
|
||||
/* instruction SRLI */
|
||||
{32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli},
|
||||
/* instruction SRAI */
|
||||
{32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai},
|
||||
/* instruction ADD */
|
||||
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
|
||||
/* instruction SUB */
|
||||
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
|
||||
/* instruction SLL */
|
||||
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
|
||||
/* instruction SLT */
|
||||
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
|
||||
/* instruction SLTU */
|
||||
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
|
||||
/* instruction XOR */
|
||||
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
|
||||
/* instruction SRL */
|
||||
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
|
||||
/* instruction SRA */
|
||||
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
|
||||
/* instruction OR */
|
||||
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
|
||||
/* instruction AND */
|
||||
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
|
||||
/* instruction FENCE */
|
||||
{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
|
||||
/* instruction FENCE_I */
|
||||
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
|
||||
/* instruction ECALL */
|
||||
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
|
||||
/* instruction EBREAK */
|
||||
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
|
||||
/* instruction URET */
|
||||
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
|
||||
/* instruction SRET */
|
||||
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
|
||||
/* instruction MRET */
|
||||
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
|
||||
/* instruction WFI */
|
||||
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
|
||||
/* instruction SFENCE.VMA */
|
||||
{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
|
||||
/* instruction CSRRW */
|
||||
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
|
||||
/* instruction CSRRS */
|
||||
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
|
||||
/* instruction CSRRC */
|
||||
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
|
||||
/* instruction CSRRWI */
|
||||
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
|
||||
/* instruction CSRRSI */
|
||||
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
|
||||
/* instruction CSRRCI */
|
||||
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
|
||||
/* instruction LWU */
|
||||
{32, 0b00000000000000000110000000000011, 0b00000000000000000111000001111111, &this_class::__lwu},
|
||||
/* instruction LD */
|
||||
{32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, &this_class::__ld},
|
||||
/* instruction SD */
|
||||
{32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, &this_class::__sd},
|
||||
/* instruction ADDIW */
|
||||
{32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, &this_class::__addiw},
|
||||
/* instruction SLLIW */
|
||||
{32, 0b00000000000000000001000000011011, 0b11111110000000000111000001111111, &this_class::__slliw},
|
||||
/* instruction SRLIW */
|
||||
{32, 0b00000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__srliw},
|
||||
/* instruction SRAIW */
|
||||
{32, 0b01000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__sraiw},
|
||||
/* instruction ADDW */
|
||||
{32, 0b00000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__addw},
|
||||
/* instruction SUBW */
|
||||
{32, 0b01000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__subw},
|
||||
/* instruction SLLW */
|
||||
{32, 0b00000000000000000001000000111011, 0b11111110000000000111000001111111, &this_class::__sllw},
|
||||
/* instruction SRLW */
|
||||
{32, 0b00000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__srlw},
|
||||
/* instruction SRAW */
|
||||
{32, 0b01000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__sraw},
|
||||
}};
|
||||
|
||||
/* instruction definitions */
|
||||
/* instruction 0: LUI */
|
||||
compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 1: AUIPC */
|
||||
compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 2: JAL */
|
||||
compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 3: JALR */
|
||||
compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 4: BEQ */
|
||||
compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 5: BNE */
|
||||
compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 6: BLT */
|
||||
compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 7: BGE */
|
||||
compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 8: BLTU */
|
||||
compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 9: BGEU */
|
||||
compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 10: LB */
|
||||
compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 11: LH */
|
||||
compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 12: LW */
|
||||
compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 13: LBU */
|
||||
compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 14: LHU */
|
||||
compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 15: SB */
|
||||
compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 16: SH */
|
||||
compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 17: SW */
|
||||
compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 18: ADDI */
|
||||
compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 19: SLTI */
|
||||
compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 20: SLTIU */
|
||||
compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 21: XORI */
|
||||
compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 22: ORI */
|
||||
compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 23: ANDI */
|
||||
compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 24: SLLI */
|
||||
compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 25: SRLI */
|
||||
compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 26: SRAI */
|
||||
compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 27: ADD */
|
||||
compile_ret_t __add(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 28: SUB */
|
||||
compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 29: SLL */
|
||||
compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 30: SLT */
|
||||
compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 31: SLTU */
|
||||
compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 32: XOR */
|
||||
compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 33: SRL */
|
||||
compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 34: SRA */
|
||||
compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 35: OR */
|
||||
compile_ret_t __or(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 36: AND */
|
||||
compile_ret_t __and(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 37: FENCE */
|
||||
compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 38: FENCE_I */
|
||||
compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 39: ECALL */
|
||||
compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 40: EBREAK */
|
||||
compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 41: URET */
|
||||
compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 42: SRET */
|
||||
compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 43: MRET */
|
||||
compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 44: WFI */
|
||||
compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 45: SFENCE.VMA */
|
||||
compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 46: CSRRW */
|
||||
compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 47: CSRRS */
|
||||
compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 48: CSRRC */
|
||||
compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 49: CSRRWI */
|
||||
compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 50: CSRRSI */
|
||||
compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 51: CSRRCI */
|
||||
compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 52: LWU */
|
||||
compile_ret_t __lwu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 53: LD */
|
||||
compile_ret_t __ld(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 54: SD */
|
||||
compile_ret_t __sd(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 55: ADDIW */
|
||||
compile_ret_t __addiw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 56: SLLIW */
|
||||
compile_ret_t __slliw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 57: SRLIW */
|
||||
compile_ret_t __srliw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 58: SRAIW */
|
||||
compile_ret_t __sraiw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 59: ADDW */
|
||||
compile_ret_t __addw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 60: SUBW */
|
||||
compile_ret_t __subw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 61: SLLW */
|
||||
compile_ret_t __sllw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 62: SRLW */
|
||||
compile_ret_t __srlw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/* instruction 63: SRAW */
|
||||
compile_ret_t __sraw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* end opcode definitions
|
||||
****************************************************************************/
|
||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, std::stringstream& os) {
|
||||
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
|
||||
this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
|
||||
get_reg_ptr(traits<ARCH>::PC), true);
|
||||
this->builder.CreateStore(
|
||||
this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
|
||||
this->gen_const(64U, 1)),
|
||||
get_reg_ptr(traits<ARCH>::ICOUNT), true);
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
this->gen_raise_trap(0, 2); // illegal instruction trap
|
||||
this->gen_sync(iss::POST_SYNC, instr_descr.size());
|
||||
this->gen_trap_check(this->leave_blk);
|
||||
return BRANCH;
|
||||
}
|
||||
};
|
||||
|
||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||
volatile CODE_WORD x = insn;
|
||||
insn = 2 * x;
|
||||
}
|
||||
|
||||
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||
|
||||
template <typename ARCH>
|
||||
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||
: vm_base<ARCH>(core, core_id, cluster_id) {
|
||||
qlut[0] = lut_00.data();
|
||||
qlut[1] = lut_01.data();
|
||||
qlut[2] = lut_10.data();
|
||||
qlut[3] = lut_11.data();
|
||||
for (auto instr : instr_descr) {
|
||||
auto quantrant = instr.value & 0x3;
|
||||
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
||||
}
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
std::tuple<continuation_e>
|
||||
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, std::ostringstrem& os) {
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
code_word_t insn = 0;
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
phys_addr_t paddr(pc);
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
paddr = this->core.v2p(pc);
|
||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
auto res = this->core.read(paddr, 2, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||
}
|
||||
} else {
|
||||
auto res = this->core.read(paddr, 4, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
}
|
||||
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
// curr pc on stack
|
||||
++inst_cnt;
|
||||
auto lut_val = extract_fields(insn);
|
||||
auto f = qlut[insn & 0x3][lut_val];
|
||||
if (f == nullptr) {
|
||||
f = &this_class::illegal_intruction;
|
||||
}
|
||||
return (this->*f)(pc, insn, this_block);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
|
||||
this->builder.SetInsertPoint(leave_blk);
|
||||
this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
|
||||
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
|
||||
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
|
||||
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
|
||||
this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
|
||||
auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
|
||||
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
|
||||
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
|
||||
this->builder.CreateCall(this->mod->getFunction("wait"), args);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
|
||||
this->builder.SetInsertPoint(trap_blk);
|
||||
auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
|
||||
get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
|
||||
this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
|
||||
this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
|
||||
auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||
this->builder.CreateRet(trap_addr_val);
|
||||
}
|
||||
|
||||
template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
|
||||
auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
|
||||
this->gen_cond_branch(this->builder.CreateICmp(
|
||||
ICmpInst::ICMP_EQ, v,
|
||||
ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
|
||||
bb, this->trap_blk, 1);
|
||||
}
|
||||
} // namespace rv64i
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::rv64i>(arch::rv64i *core, unsigned short port, bool dump) {
|
||||
auto ret = new rv64i::vm_impl<arch::rv64i>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
}
|
||||
} // namespace iss
|
||||
Reference in New Issue
Block a user