DBT-RISE/DBT-RISE-TGC
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Added entire system incl. terminal and MCP3008 ADC connected via SPI

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This commit is contained in:
Eyck Jentzsch
2018-07-23 22:15:38 +02:00
parent a899d30556
commit 100822810f
18 changed files with 423 additions and 50 deletions
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2
riscv.sc/incl/sysc/SiFive/gpio.h
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@ -83,7 +83,7 @@ protected:
private:
tlm::tlm_phase write_output(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, size_t i, sc_dt::sc_logic val);
void enable_outputs(uint32_t new_data);
void enable_outputs(uint32_t new_iof_en, uint32_t new_iof_sel);
};
} /* namespace sysc */

20
riscv.sc/incl/sysc/SiFive/spi.h
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@ -38,6 +38,11 @@
#define _SPI_H_
#include "scc/tlm_target.h"
#include "scc/signal_target_mixin.h"
#include "scc/signal_initiator_mixin.h"
#include <tlm/tlm_signal.h>
#include "cci_configuration"
#include <sysc/utils/sc_vector.h>
namespace sysc {
@ -47,15 +52,28 @@ class spi : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
sc_core::sc_in<bool> rst_i;
scc::tlm_signal_bool_opt_out sck_o;
scc::tlm_signal_bool_opt_out mosi_o;
scc::tlm_signal_bool_opt_in miso_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> scs_o;
sc_core::sc_out<bool> irq_o;
cci::cci_param<bool> bit_true_transfer;
spi(sc_core::sc_module_name nm);
virtual ~spi() override;
protected:
void clock_cb();
void reset_cb();
void transmit_data();
void receive_data(tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
void update_irq();
sc_core::sc_time clk;
std::unique_ptr<spi_regs> regs;
sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
};
} /* namespace sysc */

8
riscv.sc/incl/sysc/SiFive/uart.h
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@ -58,7 +58,7 @@ public:
sc_core::sc_out<bool> irq_o;
cci::cci_param<bool> write_to_ws;
cci::cci_param<bool> bit_true_transfer;
uart(sc_core::sc_module_name nm);
virtual ~uart() override;
@ -69,13 +69,9 @@ protected:
void transmit_data();
void receive_data(tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
void update_irq();
void before_end_of_elaboration();
sc_core::sc_time clk;
sc_core::sc_time clk{SC_ZERO_TIME},rx_last_start{SC_ZERO_TIME};
std::unique_ptr<uart_regs> regs;
sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
std::vector<uint8_t> queue;
sysc::tlm_signal_uart_extension *rx_ext, *tx_ext;
std::shared_ptr<sysc::WsHandler> handler;
};
} /* namespace sysc */