Added entire system incl. terminal and MCP3008 ADC connected via SPI

riscv.sc/incl/sysc/General/mcp3008.h

@@ -0,0 +1,47 @@
+/*
+ * mcp3008.h
+ *
+ *  Created on: 17.07.2018
+ *      Author: eyck
+ */
+
+#ifndef RISCV_SC_INCL_SYSC_GENERAL_MCP3008_H_
+#define RISCV_SC_INCL_SYSC_GENERAL_MCP3008_H_
+
+#include "scc/signal_target_mixin.h"
+#include "scc/signal_initiator_mixin.h"
+#include "sysc/tlm_extensions.h"
+#include <tlm/tlm_signal.h>
+#include "cci_configuration"
+#include <sysc/utils/sc_vector.h>
+#include <sysc/kernel/sc_module.h>
+
+namespace sysc {
+
+class mcp3008: public sc_core::sc_module {
+public:
+    SC_HAS_PROCESS(mcp3008);
+    scc::tlm_signal_logic_in  sck_i;
+    scc::tlm_signal_logic_out miso_o;
+    scc::tlm_signal_logic_in  mosi_i;
+    scc::tlm_signal_logic_in  cs_i;
+
+    sc_core::sc_in<double> vref_i;
+    sc_core::sc_vector<sc_core::sc_in<double>> ch_i;
+
+    mcp3008(sc_core::sc_module_name nm);
+    virtual ~mcp3008();
+
+private:
+    tlm::tlm_sync_enum receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
+    void do_conversion();
+    unsigned idx, rx_bits;
+    std::array<uint8_t, 3> rx_bytes, tx_bytes;
+    sc_dt::sc_logic mosi_v, miso_v, cs_v;
+    sysc::tlm_signal_spi_extension* ext, tx_ext;
+    sc_core::sc_time last_tx_start;
+};
+
+} /* namespace sysc */
+
+#endif /* RISCV_SC_INCL_SYSC_GENERAL_MCP3008_H_ */

riscv.sc/incl/sysc/General/system.h

@@ -10,6 +10,7 @@
 
 #include "sysc/SiFive/platform.h"
 #include "sysc/General/terminal.h"
+#include "sysc/General/mcp3008.h"
 #include <systemc>
 
 namespace sysc {
@@ -24,8 +25,11 @@ public:
 private:
     sc_core::sc_vector<tlm::tlm_signal<sc_dt::sc_logic>> s_gpio;
     sc_core::sc_signal<bool> s_rst_n;
+    sc_core::sc_signal<double> s_vref;
+    sc_core::sc_vector<sc_core::sc_signal<double>> s_ana;
     sysc::platform i_platform;
     sysc::terminal i_terminal;
+    sysc::mcp3008 i_adc;
     void gen_por();
 };
 

riscv.sc/incl/sysc/General/terminal.h

@@ -32,8 +32,10 @@ public:
     cci::cci_param<bool> write_to_ws;
 
 protected:
-    std::vector<uint8_t> queue;
+    void before_end_of_elaboration();
     void receive(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, sc_core::sc_time& delay);
+
+    std::vector<uint8_t> queue;
     std::shared_ptr<sysc::WsHandler> handler;
     sc_core::sc_time last_tx_start=sc_core::SC_ZERO_TIME;
 };

riscv.sc/incl/sysc/SiFive/gpio.h

@@ -83,7 +83,7 @@ protected:
 
 private:
     tlm::tlm_phase write_output(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, size_t i, sc_dt::sc_logic val);
-    void enable_outputs(uint32_t new_data);
+    void enable_outputs(uint32_t new_iof_en, uint32_t new_iof_sel);
 };
 
 } /* namespace sysc */

riscv.sc/incl/sysc/SiFive/spi.h

@@ -38,6 +38,11 @@
 #define _SPI_H_
 
 #include "scc/tlm_target.h"
+#include "scc/signal_target_mixin.h"
+#include "scc/signal_initiator_mixin.h"
+#include <tlm/tlm_signal.h>
+#include "cci_configuration"
+#include <sysc/utils/sc_vector.h>
 
 namespace sysc {
 
@@ -47,15 +52,28 @@ class spi : public sc_core::sc_module, public scc::tlm_target<> {
 public:
     SC_HAS_PROCESS(spi);
     sc_core::sc_in<sc_core::sc_time> clk_i;
-    sc_core::sc_in<bool> rst_i;
+    sc_core::sc_in<bool>             rst_i;
+    scc::tlm_signal_bool_opt_out         sck_o;
+    scc::tlm_signal_bool_opt_out         mosi_o;
+    scc::tlm_signal_bool_opt_in          miso_i;
+    sc_core::sc_vector<scc::tlm_signal_bool_opt_out> scs_o;
+
+    sc_core::sc_out<bool> irq_o;
+
+    cci::cci_param<bool> bit_true_transfer;
+
     spi(sc_core::sc_module_name nm);
     virtual ~spi() override;
 
 protected:
     void clock_cb();
     void reset_cb();
+    void transmit_data();
+    void receive_data(tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
+    void update_irq();
     sc_core::sc_time clk;
     std::unique_ptr<spi_regs> regs;
+    sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
 };
 
 } /* namespace sysc */

riscv.sc/incl/sysc/SiFive/uart.h

@@ -58,7 +58,7 @@ public:
 
     sc_core::sc_out<bool> irq_o;
 
-    cci::cci_param<bool> write_to_ws;
+    cci::cci_param<bool> bit_true_transfer;
 
     uart(sc_core::sc_module_name nm);
     virtual ~uart() override;
@@ -69,13 +69,9 @@ protected:
     void transmit_data();
     void receive_data(tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
     void update_irq();
-    void before_end_of_elaboration();
-    sc_core::sc_time clk;
+    sc_core::sc_time clk{SC_ZERO_TIME},rx_last_start{SC_ZERO_TIME};
     std::unique_ptr<uart_regs> regs;
     sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
-    std::vector<uint8_t> queue;
-    sysc::tlm_signal_uart_extension *rx_ext, *tx_ext;
-    std::shared_ptr<sysc::WsHandler> handler;
 };
 
 } /* namespace sysc */

riscv.sc/incl/sysc/tlm_extensions.h

@@ -24,6 +24,23 @@ struct tlm_signal_uart_extension : public tlm::tlm_unmanaged_extension<tlm_signa
 
 };
 
+struct tlm_signal_spi_extension : public tlm::tlm_unmanaged_extension<tlm_signal_spi_extension> {
+
+    struct spi_tx {
+        unsigned data_bits:5;
+        bool msb_first:1;
+        bool s2m_data_valid:1;
+        unsigned m2s_data, s2m_data;
+    } tx;
+    sc_core::sc_time start_time;
+
+    void copy_from(tlm_extension_base const & other) override {
+        auto& o = static_cast<const type&>(other);
+        this->tx=o.tx;
+        this->start_time=o.start_time;
+    }
+};
+
 }