get all compile clean

CMakeLists.txt

@@ -44,19 +44,28 @@ add_subdirectory(softfloat)
 FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
 set(LIB_HEADERS ${RiscVSCHeaders} )
 set(LIB_SOURCES 
-	#src/iss/rv32gc.cpp
+	src/iss/rv32gc.cpp
 	src/iss/rv32imac.cpp
-	#src/iss/rv64i.cpp
+	src/iss/rv64i.cpp
-	#src/iss/rv64gc.cpp
+	src/iss/rv64gc.cpp
 	src/iss/mnrv32.cpp
-	src/vm/llvm/fp_functions.cpp
+	src/vm/fp_functions.cpp
+	src/vm/llvm/fp_impl.cpp
 	src/vm/llvm/vm_mnrv32.cpp
-	#src/vm/llvm/vm_rv32gc.cpp
+	src/vm/llvm/vm_rv32gc.cpp
-	#src/vm/llvm/vm_rv32imac.cpp
+	src/vm/llvm/vm_rv32imac.cpp
-	#src/vm/llvm/vm_rv64i.cpp
+	src/vm/llvm/vm_rv64i.cpp
-	#src/vm/llvm/vm_rv64gc.cpp
+	src/vm/llvm/vm_rv64gc.cpp
 	src/vm/tcc/vm_mnrv32.cpp
+	src/vm/tcc/vm_rv32gc.cpp
+	src/vm/tcc/vm_rv32imac.cpp
+	src/vm/tcc/vm_rv64i.cpp
+	src/vm/tcc/vm_rv64gc.cpp
 	src/vm/interp/vm_mnrv32.cpp
+	src/vm/interp/vm_rv32gc.cpp
+	src/vm/interp/vm_rv32imac.cpp
+	src/vm/interp/vm_rv64i.cpp
+	src/vm/interp/vm_rv64gc.cpp
     src/plugin/instruction_count.cpp
     src/plugin/cycle_estimate.cpp)
 

gen_input/RVF.core_desc

@@ -376,7 +376,7 @@ InsructionSet RV64F extends RV32F{
         FCVT.S.L { // 64bit signed int to to fp 
             encoding: b1101000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
             args_disass:"f{rd}, x{rs1}";
-            val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32));
+            val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32), rm{8});
             if(FLEN==32)
                 F[rd] <= res;
             else { // NaN boxing
@@ -387,7 +387,7 @@ InsructionSet RV64F extends RV32F{
         FCVT.S.LU { // 64bit unsigned int to to fp 
             encoding: b1101000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
             args_disass:"f{rd}, x{rs1}";
-            val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32));
+            val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32), rm{8});
             if(FLEN==32)
                 F[rd] <= res;
             else { // NaN boxing

gen_input/minres_rv.core_desc

@@ -17,7 +17,7 @@ Core MNRV32 provides RV32I, RV32IC {
         PGMASK := 0xfff; //PGSIZE-1
     }
 }
-/*
+
 Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
     constants {
         XLEN:=32;
@@ -67,4 +67,4 @@ Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
         PGMASK := 0xfff; //PGSIZE-1
     }
 }
-*/
+

gen_input/templates/interp/incl-CORENAME.h.gtl

@@ -172,6 +172,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline bool should_stop() { return interrupt_sim; }
 
+    inline uint64_t stop_code() { return interrupt_sim; }
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
                 addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
@@ -204,7 +206,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
-    bool interrupt_sim=false;
+    uint64_t interrupt_sim=0;
 <%
 def fcsr = allRegs.find {it.name=='FCSR'}
 if(fcsr != null) {%>

gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl

@@ -30,6 +30,7 @@
  *
  *******************************************************************************/
 
+#include "../fp_functions.h"
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/debugger/gdb_session.h>

gen_input/templates/llvm/incl-CORENAME.h.gtl

@@ -172,6 +172,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline bool should_stop() { return interrupt_sim; }
 
+    inline uint64_t stop_code() { return interrupt_sim; }
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
                 addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
@@ -204,7 +206,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
-    bool interrupt_sim=false;
+    uint64_t interrupt_sim=0;
 <%
 def fcsr = allRegs.find {it.name=='FCSR'}
 if(fcsr != null) {%>

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -57,7 +57,7 @@ using namespace ::llvm;
 using namespace iss::arch;
 using namespace iss::debugger;
 
-template <typename ARCH> class vm_impl : public vm::llvm::vm_base<ARCH> {
+template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
 public:
     using super = typename iss::llvm::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;

incl/iss/arch/rv32gc.h

@@ -215,6 +215,8 @@ struct rv32gc: public arch_if {
 
     inline bool should_stop() { return interrupt_sim; }
 
+    inline uint64_t stop_code() { return interrupt_sim; }
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if (addr.space != traits<rv32gc>::MEM || addr.type == iss::address_type::PHYSICAL ||
                 addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
@@ -304,7 +306,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
-    bool interrupt_sim=false;
+    uint64_t interrupt_sim=0;
 
 	uint32_t get_fcsr(){return reg.FCSR;}
 	void set_fcsr(uint32_t val){reg.FCSR = val;}		

incl/iss/arch/rv32imac.h

@@ -182,6 +182,8 @@ struct rv32imac: public arch_if {
 
     inline bool should_stop() { return interrupt_sim; }
 
+    inline uint64_t stop_code() { return interrupt_sim; }
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if (addr.space != traits<rv32imac>::MEM || addr.type == iss::address_type::PHYSICAL ||
                 addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
@@ -238,7 +240,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
-    bool interrupt_sim=false;
+    uint64_t interrupt_sim=0;
 
 	uint32_t get_fcsr(){return 0;}
 	void set_fcsr(uint32_t val){}

incl/iss/arch/rv64gc.h

@@ -215,6 +215,8 @@ struct rv64gc: public arch_if {
 
     inline bool should_stop() { return interrupt_sim; }
 
+    inline uint64_t stop_code() { return interrupt_sim; }
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if (addr.space != traits<rv64gc>::MEM || addr.type == iss::address_type::PHYSICAL ||
                 addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
@@ -304,7 +306,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
-    bool interrupt_sim=false;
+    uint64_t interrupt_sim=0;
 
 	uint32_t get_fcsr(){return reg.FCSR;}
 	void set_fcsr(uint32_t val){reg.FCSR = val;}		

incl/iss/arch/rv64i.h

@@ -182,6 +182,8 @@ struct rv64i: public arch_if {
 
     inline bool should_stop() { return interrupt_sim; }
 
+    inline uint64_t stop_code() { return interrupt_sim; }
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if (addr.space != traits<rv64i>::MEM || addr.type == iss::address_type::PHYSICAL ||
                 addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
@@ -238,7 +240,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
-    bool interrupt_sim=false;
+    uint64_t interrupt_sim=0;
 
 	uint32_t get_fcsr(){return 0;}
 	void set_fcsr(uint32_t val){}

src/main.cpp

@@ -36,6 +36,10 @@
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/rv32imac.h>
+#include <iss/arch/rv32gc.h>
+#include <iss/arch/rv64gc.h>
+#include <iss/arch/rv64i.h>
 #include <iss/arch/mnrv32.h>
 #include <iss/llvm/jit_helper.h>
 #include <iss/log_categories.h>
@@ -44,6 +48,21 @@
 
 namespace po = boost::program_options;
 
+using cpu_ptr = std::unique_ptr<iss::arch_if>;
+using vm_ptr= std::unique_ptr<iss::vm_if>;
+
+template<typename CORE>
+std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
+    CORE* lcpu = new iss::arch::riscv_hart_msu_vp<CORE>();
+    if(backend == "interp")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+    if(backend == "llvm")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+    if(backend == "tcc")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+    return {nullptr, nullptr};
+}
+
 int main(int argc, char *argv[]) {
     /*
      *  Define and parse the program options
@@ -104,17 +123,23 @@ int main(int argc, char *argv[]) {
         iss::init_jit_debug(argc, argv);
         bool dump = clim.count("dump-ir");
         // instantiate the simulator
-        std::unique_ptr<iss::vm_if> vm{nullptr};
+        vm_ptr vm{nullptr};
-        std::unique_ptr<iss::arch_if> cpu{nullptr};
+        cpu_ptr cpu{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
-        iss::arch::mnrv32* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::mnrv32>();
+        if (isa_opt=="mnrv32") {
-        if(clim["backend"].as<std::string>() == "interp")
+            std::tie(cpu, vm) = create_cpu<iss::arch::mnrv32>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-            vm = iss::interp::create(lcpu, clim["gdb-port"].as<unsigned>());
+        } else if (isa_opt=="rv64i") {
-        if(clim["backend"].as<std::string>() == "llvm")
+            std::tie(cpu, vm) = create_cpu<iss::arch::rv64i>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-            vm = iss::llvm::create(lcpu, clim["gdb-port"].as<unsigned>());
+//        } else if (isa_opt=="rv64gc") {
-        if(clim["backend"].as<std::string>() == "tcc")
+//            std::tie(cpu, vm) = create_cpu<iss::arch::rv64gc>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-            vm = iss::tcc::create(lcpu, clim["gdb-port"].as<unsigned>());
+//        } else if (isa_opt=="rv32imac") {
-        cpu.reset(lcpu);
+//            std::tie(cpu, vm) = create_cpu<iss::arch::rv32imac>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+//        } else if (isa_opt=="rv32gc") {
+//            std::tie(cpu, vm) = create_cpu<iss::arch::rv32gc>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else {
+            LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
+            return 127;
+        }
         if (clim.count("plugin")) {
             for (std::string opt_val : clim["plugin"].as<std::vector<std::string>>()) {
                 std::string plugin_name{opt_val};

src/vm/fp_functions.cpp

@@ -32,8 +32,7 @@
 //       eyck@minres.com - initial API and implementation
 ////////////////////////////////////////////////////////////////////////////////
 
-#include <iss/iss.h>
+#include "fp_functions.h"
-#include <iss/llvm/vm_base.h>
 
 extern "C" {
 #include <softfloat.h>
@@ -43,71 +42,6 @@ extern "C" {
 
 #include <limits>
 
-namespace iss {
-namespace llvm {
-namespace fp_impl {
-
-using namespace std;
-using namespace ::llvm;
-
-#define INT_TYPE(L)   Type::getIntNTy(mod->getContext(), L)
-#define FLOAT_TYPE    Type::getFloatTy(mod->getContext())
-#define DOUBLE_TYPE   Type::getDoubleTy(mod->getContext())
-#define VOID_TYPE     Type::getVoidTy(mod->getContext())
-#define THIS_PTR_TYPE Type::getIntNPtrTy(mod->getContext(), 8)
-#define FDECLL(NAME, RET, ...)                                                                                         \
-    Function *NAME##_func = CurrentModule->getFunction(#NAME);                                                         \
-    if (!NAME##_func) {                                                                                                \
-        std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                  \
-        FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                        \
-        NAME##_func = Function::Create(NAME##_type, GlobalValue::ExternalLinkage, #NAME, CurrentModule);               \
-        NAME##_func->setCallingConv(CallingConv::C);                                                                   \
-    }
-
-#define FDECL(NAME, RET, ...)                                                                                          \
-    std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                      \
-    FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                      \
-    mod->getOrInsertFunction(#NAME, NAME##_type);
-
-
-void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
-    if(flen){
-        FDECL(fget_flags, INT_TYPE(32));
-        FDECL(fadd_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fsub_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fmul_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fdiv_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fsqrt_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fcmp_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
-        FDECL(fcvt_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fmadd_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fsel_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
-        FDECL(fclass_s,   INT_TYPE(32), INT_TYPE(32));
-        FDECL(fcvt_32_64,     INT_TYPE(64), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
-        FDECL(fcvt_64_32,     INT_TYPE(32), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
-        if(flen>32){
-            FDECL(fconv_d2f,  INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
-            FDECL(fconv_f2d,  INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
-            FDECL(fadd_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
-            FDECL(fsub_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
-            FDECL(fmul_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
-            FDECL(fdiv_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
-            FDECL(fsqrt_d,    INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
-            FDECL(fcmp_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
-            FDECL(fcvt_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
-            FDECL(fmadd_d,    INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
-            FDECL(fsel_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
-            FDECL(fclass_d,   INT_TYPE(64), INT_TYPE(64));
-            FDECL(unbox_s,      INT_TYPE(32), INT_TYPE(64));
-
-        }
-    }
-}
-
-}
-}
-}
-
 using this_t = uint8_t *;
 const uint8_t rmm_map[] = {
         softfloat_round_near_even /*RNE*/,

src/vm/fp_functions.h

@@ -0,0 +1,68 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2020, MINRES Technologies GmbH
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+//    this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright notice,
+//    this list of conditions and the following disclaimer in the documentation
+//    and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its contributors
+//    may be used to endorse or promote products derived from this software
+//    without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// Contributors:
+//       eyck@minres.com - initial API and implementation
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _VM_FP_FUNCTIONS_H_
+#define _VM_FP_FUNCTIONS_H_
+
+#include <stdint.h>
+
+extern "C" {
+uint32_t fget_flags();
+uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode);
+uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode);
+uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode);
+uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode);
+uint32_t fsqrt_s(uint32_t v1, uint8_t mode);
+uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) ;
+uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode);
+uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode);
+uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op);
+uint32_t fclass_s( uint32_t v1 );
+uint32_t fconv_d2f(uint64_t v1, uint8_t mode);
+uint64_t fconv_f2d(uint32_t v1, uint8_t mode);
+uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode);
+uint64_t fsub_d(uint64_t v1, uint64_t v2, uint8_t mode);
+uint64_t fmul_d(uint64_t v1, uint64_t v2, uint8_t mode);
+uint64_t fdiv_d(uint64_t v1, uint64_t v2, uint8_t mode);
+uint64_t fsqrt_d(uint64_t v1, uint8_t mode);
+uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op);
+uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode);
+uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode);
+uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) ;
+uint64_t fclass_d(uint64_t v1  );
+uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode);
+uint32_t fcvt_64_32(uint64_t v1, uint32_t op, uint8_t mode);
+uint32_t unbox_s(uint64_t v);
+}
+#endif /* RISCV_SRC_VM_FP_FUNCTIONS_H_ */

src/vm/interp/vm_mnrv32.cpp

@@ -30,6 +30,7 @@
  *
  *******************************************************************************/
 
+#include "../fp_functions.h"
 #include <iss/arch/mnrv32.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/debugger/gdb_session.h>

src/vm/llvm/fp_impl.cpp

@@ -0,0 +1,109 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2017, MINRES Technologies GmbH
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+//    this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright notice,
+//    this list of conditions and the following disclaimer in the documentation
+//    and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its contributors
+//    may be used to endorse or promote products derived from this software
+//    without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// Contributors:
+//       eyck@minres.com - initial API and implementation
+////////////////////////////////////////////////////////////////////////////////
+
+#include <iss/iss.h>
+#include <iss/llvm/vm_base.h>
+
+extern "C" {
+#include <softfloat.h>
+#include "internals.h"
+#include "specialize.h"
+}
+
+#include <limits>
+
+namespace iss {
+namespace llvm {
+namespace fp_impl {
+
+using namespace std;
+using namespace ::llvm;
+
+#define INT_TYPE(L)   Type::getIntNTy(mod->getContext(), L)
+#define FLOAT_TYPE    Type::getFloatTy(mod->getContext())
+#define DOUBLE_TYPE   Type::getDoubleTy(mod->getContext())
+#define VOID_TYPE     Type::getVoidTy(mod->getContext())
+#define THIS_PTR_TYPE Type::getIntNPtrTy(mod->getContext(), 8)
+#define FDECLL(NAME, RET, ...)                                                                                         \
+    Function *NAME##_func = CurrentModule->getFunction(#NAME);                                                         \
+    if (!NAME##_func) {                                                                                                \
+        std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                  \
+        FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                        \
+        NAME##_func = Function::Create(NAME##_type, GlobalValue::ExternalLinkage, #NAME, CurrentModule);               \
+        NAME##_func->setCallingConv(CallingConv::C);                                                                   \
+    }
+
+#define FDECL(NAME, RET, ...)                                                                                          \
+    std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                      \
+    FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                      \
+    mod->getOrInsertFunction(#NAME, NAME##_type);
+
+
+void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
+    if(flen){
+        FDECL(fget_flags, INT_TYPE(32));
+        FDECL(fadd_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fsub_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fmul_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fdiv_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fsqrt_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fcmp_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
+        FDECL(fcvt_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fmadd_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fsel_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
+        FDECL(fclass_s,   INT_TYPE(32), INT_TYPE(32));
+        FDECL(fcvt_32_64,     INT_TYPE(64), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(fcvt_64_32,     INT_TYPE(32), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+        if(flen>32){
+            FDECL(fconv_d2f,  INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
+            FDECL(fconv_f2d,  INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+            FDECL(fadd_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(fsub_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(fmul_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(fdiv_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(fsqrt_d,    INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(fcmp_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
+            FDECL(fcvt_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+            FDECL(fmadd_d,    INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+            FDECL(fsel_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
+            FDECL(fclass_d,   INT_TYPE(64), INT_TYPE(64));
+            FDECL(unbox_s,      INT_TYPE(32), INT_TYPE(64));
+
+        }
+    }
+}
+
+}
+}
+}

src/vm/llvm/vm_rv64i.cpp

@@ -49,17 +49,15 @@
 namespace iss {
 namespace llvm {
 namespace fp_impl {
-void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
+void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
-}
 }
 
 namespace rv64i {
+using namespace ::llvm;
 using namespace iss::arch;
-using namespace llvm;
 using namespace iss::debugger;
-using namespace iss::llvm;
 
-template <typename ARCH> class vm_impl : public vm_base<ARCH> {
+template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
 public:
     using super = typename iss::llvm::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
@@ -3150,5 +3148,5 @@ std::unique_ptr<vm_if> create<arch::rv64i>(arch::rv64i *core, unsigned short por
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-
+} // namespace llvm
 } // namespace iss