get all compile clean
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@ -376,7 +376,7 @@ InsructionSet RV64F extends RV32F{
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FCVT.S.L { // 64bit signed int to to fp
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encoding: b1101000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, x{rs1}";
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val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32));
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val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32), rm{8});
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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@ -387,7 +387,7 @@ InsructionSet RV64F extends RV32F{
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FCVT.S.LU { // 64bit unsigned int to to fp
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encoding: b1101000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, x{rs1}";
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val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32));
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val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32), rm{8});
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if(FLEN==32)
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F[rd] <= res;
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else { // NaN boxing
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