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adds functionality, adds working asmjit

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Eyck-Alexander Jentzsch
2023-11-20 11:45:52 +01:00
parent e48597b2b7
commit 0eb1db0e7e
5 changed files with 2114 additions and 1883 deletions
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5
src/iss/arch/riscv_hart_m_p.h
View File

@ -320,6 +320,8 @@ protected:
unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
riscv_hart_m_p<BASE, FEAT>& arch;
};
@ -822,7 +824,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
x |= 0x80; // set pll lock upon writing
return iss::Ok;
} break;
default: {}
default: {
}
}
} break;
case traits<BASE>::CSR: {

11
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -371,6 +371,8 @@ protected:
unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
riscv_hart_msu_vp<BASE>& arch;
};
@ -802,7 +804,8 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
x |= 0x80; // set pll lock upon writing
return iss::Ok;
} break;
default: {}
default: {
}
}
} break;
case traits<BASE>::CSR: {
@ -1225,9 +1228,9 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
break;
} else if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
break;
} else if(type == iss::access_type::FETCH ? !(pte & PTE_X)
: type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
: !((pte & PTE_R) && (pte & PTE_W))) {
} else if(type == iss::access_type::FETCH ? !(pte & PTE_X)
: type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
: !((pte & PTE_R) && (pte & PTE_W))) {
break;
} else if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
break;

5
src/iss/arch/riscv_hart_mu_p.h
View File

@ -347,6 +347,8 @@ protected:
unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
riscv_hart_mu_p<BASE, FEAT>& arch;
};
@ -1005,7 +1007,8 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
x |= 0x80; // set pll lock upon writing
return iss::Ok;
} break;
default: {}
default: {
}
}
} break;
case traits<BASE>::CSR: {