DBT-RISE-TGC/src_test/iss/arch/tgc5a.h

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#ifndef _TGC5A_H_
#define _TGC5A_H_
// clang-format off
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>

namespace iss {
namespace arch {

struct tgc5a;

template <> struct traits<tgc5a> {

    constexpr static char const* const core_type = "TGC5A";
    
    static constexpr std::array<const char*, 20> reg_names{
        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "pc", "next_pc", "priv", "dpc"}};
 
    static constexpr std::array<const char*, 20> reg_aliases{
        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "pc", "next_pc", "priv", "dpc"}};

    enum constants {MISA_VAL=1073741840ULL, MARCHID_VAL=2147483649ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=16ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL};

    constexpr static unsigned FP_REGS_SIZE = 0;

    enum reg_e {
        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
    };

    using reg_t = uint32_t;

    using addr_t = uint32_t;

    using code_word_t = uint32_t; //TODO: check removal

    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;

    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;

    static constexpr std::array<const uint32_t, 27> reg_bit_widths{
        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};

    static constexpr std::array<const uint32_t, 27> reg_byte_offsets{
        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,73,77,81,85,93,101,109,113}};

    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);

    enum sreg_flag_e { FLAGS };

    enum mem_type_e { MEM, FENCE, RES, CSR };
    
    enum class opcode_e {
        LUI = 0,
        AUIPC = 1,
        JAL = 2,
        JALR = 3,
        BEQ = 4,
        BNE = 5,
        BLT = 6,
        BGE = 7,
        BLTU = 8,
        BGEU = 9,
        LB = 10,
        LH = 11,
        LW = 12,
        LBU = 13,
        LHU = 14,
        SB = 15,
        SH = 16,
        SW = 17,
        ADDI = 18,
        SLTI = 19,
        SLTIU = 20,
        XORI = 21,
        ORI = 22,
        ANDI = 23,
        SLLI = 24,
        SRLI = 25,
        SRAI = 26,
        ADD = 27,
        SUB = 28,
        SLL = 29,
        SLT = 30,
        SLTU = 31,
        XOR = 32,
        SRL = 33,
        SRA = 34,
        OR = 35,
        AND = 36,
        FENCE = 37,
        ECALL = 38,
        EBREAK = 39,
        MRET = 40,
        WFI = 41,
        CSRRW = 42,
        CSRRS = 43,
        CSRRC = 44,
        CSRRWI = 45,
        CSRRSI = 46,
        CSRRCI = 47,
        FENCE_I = 48,
        MAX_OPCODE
    };
};

struct tgc5a: public arch_if {

    using virt_addr_t = typename traits<tgc5a>::virt_addr_t;
    using phys_addr_t = typename traits<tgc5a>::phys_addr_t;
    using reg_t =  typename traits<tgc5a>::reg_t;
    using addr_t = typename traits<tgc5a>::addr_t;

    tgc5a();
    ~tgc5a();

    void reset(uint64_t address=0) override;

    uint8_t* get_regs_base_ptr() override;

    inline uint64_t get_icount() { return reg.icount; }

    inline bool should_stop() { return interrupt_sim; }

    inline uint64_t stop_code() { return interrupt_sim; }

    virtual phys_addr_t virt2phys(const iss::addr_t& addr);

    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }

    inline uint32_t get_last_branch() { return reg.last_branch; }


#pragma pack(push, 1)
    struct TGC5A_regs { 
        uint32_t X0 = 0; 
        uint32_t X1 = 0; 
        uint32_t X2 = 0; 
        uint32_t X3 = 0; 
        uint32_t X4 = 0; 
        uint32_t X5 = 0; 
        uint32_t X6 = 0; 
        uint32_t X7 = 0; 
        uint32_t X8 = 0; 
        uint32_t X9 = 0; 
        uint32_t X10 = 0; 
        uint32_t X11 = 0; 
        uint32_t X12 = 0; 
        uint32_t X13 = 0; 
        uint32_t X14 = 0; 
        uint32_t X15 = 0; 
        uint32_t PC = 0; 
        uint32_t NEXT_PC = 0; 
        uint8_t PRIV = 0; 
        uint32_t DPC = 0;
        uint32_t trap_state = 0, pending_trap = 0;
        uint64_t icount = 0;
        uint64_t cycle = 0;
        uint64_t instret = 0;
        uint32_t instruction = 0;
        uint32_t last_branch = 0;
    } reg;
#pragma pack(pop)
    std::array<address_type, 4> addr_mode;
    
    uint64_t interrupt_sim=0;

    uint32_t get_fcsr(){return 0;}
    void set_fcsr(uint32_t val){}

};

}
}            
#endif /* _TGC5A_H_ */
// clang-format on