DBT-RISE-TGC/riscv.sc/src/sysc/spi.cpp

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////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
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//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
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//
// http://www.apache.org/licenses/LICENSE-2.0
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//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/spi.h"
#include "sysc/SiFive/gen/spi_regs.h"
#include "sysc/utilities.h"
namespace sysc {
spi::spi(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm), tlm_target<>(clk), NAMED(clk_i), NAMED(rst_i), NAMEDD(spi_regs, regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
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sensitive << clk_i;
SC_METHOD(reset_cb);
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sensitive << rst_i;
}
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spi::~spi() {}
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void spi::clock_cb() { this->clk = clk_i.read(); }
void spi::reset_cb() {
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if (rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */