101 lines
3.6 KiB
C
101 lines
3.6 KiB
C
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/*******************************************************************************
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* Copyright (C) 2022 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contributors:
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* eyck@minres.com - initial implementation
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******************************************************************************/
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#ifndef _RISCV_HART_M_P_HWL_H
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#define _RISCV_HART_M_P_HWL_H
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#include <iss/vm_types.h>
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namespace iss {
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namespace arch {
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template <typename BASE> class hwl : public BASE {
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public:
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using base_class = BASE;
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using this_class = hwl<BASE>;
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using reg_t = typename BASE::reg_t;
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hwl();
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virtual ~hwl() = default;
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protected:
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iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
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iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
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};
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template<typename BASE>
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inline hwl<BASE>::hwl() {
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for (unsigned addr = 0x800; addr < 0x803; ++addr){
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this->register_custom_csr_rd(addr);
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this->register_custom_csr_wr(addr);
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}
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for (unsigned addr = 0x804; addr < 0x807; ++addr){
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this->register_custom_csr_rd(addr);
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this->register_custom_csr_wr(addr);
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}
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}
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template<typename BASE>
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inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
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switch(addr){
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case 0x800: val = this->reg.lpstart0; break;
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case 0x801: val = this->reg.lpend0; break;
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case 0x802: val = this->reg.lpcount0; break;
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case 0x804: val = this->reg.lpstart1; break;
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case 0x805: val = this->reg.lpend1; break;
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case 0x806: val = this->reg.lpcount1; break;
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}
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return iss::Ok;
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}
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template<typename BASE>
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inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
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switch(addr){
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case 0x800: this->reg.lpstart0 = val; break;
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case 0x801: this->reg.lpend0 = val; break;
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case 0x802: this->reg.lpcount0 = val; break;
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case 0x804: this->reg.lpstart1 = val; break;
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case 0x805: this->reg.lpend1 = val; break;
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case 0x806: this->reg.lpcount1 = val; break;
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}
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return iss::Ok;
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}
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} // namespace arch
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} // namespace iss
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#endif /* _RISCV_HART_M_P_H */
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