DBT-RISE/CoreDSL2JSON
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Eyck Jentzsch
2021-09-25 16:22:15 +02:00
commit 07831ef4fc
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69
com.minres.coredsl.json.tests/inputs/core_1.core_desc Normal file
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Core TGC_X {
architectural_state {
unsigned int XLEN=32, FLEN=32;
unsigned CSR_SIZE = 4096;
unsigned REG_FILE_SIZE=32;
unsigned fencei=1;
register unsigned PC [[is_pc]];
register unsigned X[REG_FILE_SIZE];
extern char MEM[1<<XLEN];
extern unsigned CSR[CSR_SIZE];
extern unsigned<XLEN> FENCE;
}
instructions {
ADDI [[hls]] {
encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] + imm;
}
}
SLTI {
encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] < imm? 1 : 0;
}
}
SW {
encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
behavior: {
int offset = X[rs1] + imm;
MEM[offset] = X[rs2];
}
}
LW {
encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
behavior: if(rd!=0) X[rd]=(int)MEM[X[rs1] + imm];
}
LB {
encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
behavior: if(rd!=0) X[rd]=MEM[X[rs1] + imm];
}
LBU {
encoding: imm[11:0] :: rs1[4:0] :: 0b100 :: rd[4:0] :: 0b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
behavior: if(rd!=0) X[rd]=(unsigned char)MEM[X[rs1] + imm];
}
JAL[[no_cont]] {
encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
behavior: {
if(rd!=0) X[rd] = (unsigned)PC;
PC = PC+imm;
}
}
CSRRCI {
encoding: csr[11:0] :: zimm[4:0] :: 0b111 :: rd[4:0] :: 0b1110011;
args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
behavior: {
unsigned<XLEN> res = CSR[csr];
if(rd!=0) X[rd] = res;
if(zimm!=0) CSR[csr] = res & ~((unsigned<XLEN>)zimm);
}
}
FENCE_I[[flush]] {
encoding: imm[11:0] :: rs1[4:0] :: 0b001 :: rd[4:0] :: 0b0001111 ;
behavior: FENCE[fencei] = imm;
}
}
}

47
com.minres.coredsl.json.tests/inputs/isa_1.core_desc Normal file
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InstructionSet RV32I {
architectural_state {
unsigned int XLEN=32, FLEN=32;
unsigned CSR_SIZE = 4096;
unsigned REG_FILE_SIZE=32;
unsigned fencei=1;
register unsigned PC [[is_pc]];
register unsigned X[REG_FILE_SIZE];
extern char MEM[1<<XLEN];
extern unsigned CSR[CSR_SIZE];
extern unsigned<XLEN> FENCE;
}
instructions [[hls]]{
ADDI [[flush]]{
encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] + imm;
}
}
SLTI {
encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] < imm? 1 : 0;
}
}
SLTIU {
encoding: imm[11:0] :: rs1[4:0] :: 0b011 :: rd[4:0] :: 0b0010011;
behavior: {
X[rd] = X[rs1] < imm? 1 : 0;
}
}
SW {
encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
behavior: {
int offset = X[rs1] + imm;
MEM[offset] = X[rs2];
}
}
JAL[[no_cont]] {
encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
behavior: {
if(rd!=0) X[rd] = (unsigned)PC;
PC = PC+imm;
}
}
}
}