70 lines
2.4 KiB
Plaintext
70 lines
2.4 KiB
Plaintext
Core TGC_X {
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architectural_state {
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unsigned int XLEN=32, FLEN=32;
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unsigned CSR_SIZE = 4096;
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unsigned REG_FILE_SIZE=32;
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unsigned fencei=1;
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register unsigned PC [[is_pc]];
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register unsigned X[REG_FILE_SIZE];
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extern char MEM[1<<XLEN];
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extern unsigned CSR[CSR_SIZE];
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extern unsigned<XLEN> FENCE;
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}
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instructions {
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ADDI [[hls]] {
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encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] + imm;
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}
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}
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SLTI {
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encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] < imm? 1 : 0;
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}
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}
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SW {
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encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
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behavior: {
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int offset = X[rs1] + imm;
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MEM[offset] = X[rs2];
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}
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}
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LW {
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encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0000011;
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args_disass:"{name(rd)}, {imm}({name(rs1)})";
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behavior: if(rd!=0) X[rd]=(int)MEM[X[rs1] + imm];
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}
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LB {
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encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0000011;
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args_disass:"{name(rd)}, {imm}({name(rs1)})";
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behavior: if(rd!=0) X[rd]=MEM[X[rs1] + imm];
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}
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LBU {
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encoding: imm[11:0] :: rs1[4:0] :: 0b100 :: rd[4:0] :: 0b0000011;
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args_disass:"{name(rd)}, {imm}({name(rs1)})";
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behavior: if(rd!=0) X[rd]=(unsigned char)MEM[X[rs1] + imm];
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}
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JAL[[no_cont]] {
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encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
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behavior: {
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if(rd!=0) X[rd] = (unsigned)PC;
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PC = PC+imm;
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}
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}
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CSRRCI {
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encoding: csr[11:0] :: zimm[4:0] :: 0b111 :: rd[4:0] :: 0b1110011;
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args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
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behavior: {
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unsigned<XLEN> res = CSR[csr];
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if(rd!=0) X[rd] = res;
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if(zimm!=0) CSR[csr] = res & ~((unsigned<XLEN>)zimm);
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}
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}
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FENCE_I[[flush]] {
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encoding: imm[11:0] :: rs1[4:0] :: 0b001 :: rd[4:0] :: 0b0001111 ;
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behavior: FENCE[fencei] = imm;
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}
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}
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}
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