48 lines
1.4 KiB
Plaintext
48 lines
1.4 KiB
Plaintext
InstructionSet RV32I {
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architectural_state {
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unsigned int XLEN=32, FLEN=32;
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unsigned CSR_SIZE = 4096;
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unsigned REG_FILE_SIZE=32;
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unsigned fencei=1;
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register unsigned PC [[is_pc]];
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register unsigned X[REG_FILE_SIZE];
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extern char MEM[1<<XLEN];
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extern unsigned CSR[CSR_SIZE];
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extern unsigned<XLEN> FENCE;
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}
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instructions [[hls]]{
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ADDI [[flush]]{
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encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] + imm;
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}
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}
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SLTI {
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encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] < imm? 1 : 0;
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}
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}
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SLTIU {
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encoding: imm[11:0] :: rs1[4:0] :: 0b011 :: rd[4:0] :: 0b0010011;
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behavior: {
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X[rd] = X[rs1] < imm? 1 : 0;
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}
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}
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SW {
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encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
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behavior: {
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int offset = X[rs1] + imm;
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MEM[offset] = X[rs2];
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}
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}
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JAL[[no_cont]] {
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encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
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behavior: {
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if(rd!=0) X[rd] = (unsigned)PC;
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PC = PC+imm;
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}
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}
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}
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}
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