InstructionSet RV32I {
 	architectural_state {
        unsigned int XLEN=32, FLEN=32;
        unsigned CSR_SIZE = 4096;
        unsigned REG_FILE_SIZE=32;
        unsigned fencei=1;
    	register unsigned PC [[is_pc]];
        register unsigned X[REG_FILE_SIZE];
        extern char MEM[1<<XLEN];
        extern unsigned CSR[CSR_SIZE];
        extern unsigned<XLEN> FENCE;
    }
    instructions [[hls]]{ 
       ADDI [[flush]]{
            encoding: imm[11:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0010011;
            behavior: {
            	X[rd] = X[rs1] + imm;            
            }
        }
        SLTI {
            encoding: imm[11:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0010011;
            behavior: {
	            X[rd] = X[rs1] < imm? 1 : 0;	            
            }
        }
        SLTIU {
            encoding: imm[11:0] :: rs1[4:0] :: 0b011 :: rd[4:0] :: 0b0010011;
            behavior: {
	            X[rd] = X[rs1] < imm? 1 : 0;
            }
        }
        SW {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 0b010 :: imm[4:0] :: 0b0100011;
            behavior: {
	            int offset =  X[rs1] + imm;
	            MEM[offset] = X[rs2];
            }
        }
        JAL[[no_cont]] {
            encoding:imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 0b1101111;
            behavior: {
                if(rd!=0) X[rd] = (unsigned)PC;
                PC = PC+imm;
            }
        }
    }
}