avoid interrupts while printing

raven_spn/src/init.h

@@ -12,8 +12,8 @@ typedef void (*function_ptr_t) (void);
 //! Instance data for the PLIC.
 plic_instance_t g_plic;
 std::array<function_ptr_t,PLIC_NUM_INTERRUPTS>  g_ext_interrupt_handlers;
-bool spn1_hw_interrupt{true};
+volatile bool spn1_hw_interrupt{true};
-bool spn2_hw_interrupt{true};
+volatile bool spn2_hw_interrupt{true};
 
 
 /*! \brief external interrupt handler
@@ -45,36 +45,38 @@ void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1)
 }
 
 void wait_for_spn1_interrupt() {
-    // wait until HW is done
+    // This is a time critical part. It must be ensured that no interrupt is processed between flag checking and wfi.
-    if(spn1_hw_interrupt) {
+    // Disable interrupts and wait a few more clocks for the instruction to take effect before checking the flag.
-        do{
+    asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
-            asm("wfi");
+    while(spn1_hw_interrupt) {
-            asm("nop");
+        // Enable interrupts and immediately enter wfi.
-        }while(spn1_hw_interrupt);
+        asm volatile ("csrrs x0, mie, %0; wfi; nop" : : "r"(MIP_MEIP));
+        // Disable interrupts again before examine the flag value.
+        asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
     }
 	spn1_hw_interrupt=true;
+    set_csr(mie, MIP_MEIP);
 }
 
 void wait_for_spn2_interrupt() {
-    // wait until HW is done
+    asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
-    if(spn2_hw_interrupt) {
+    while(spn2_hw_interrupt) {
-        do{
+        asm volatile ("csrrs x0, mie, %0; wfi; nop" : : "r"(MIP_MEIP));
-            asm("wfi");
+        asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
-            asm("nop");
-        }while(spn2_hw_interrupt);
     }
     spn2_hw_interrupt=true;
+    set_csr(mie, MIP_MEIP);
 }
 
 void wait_for_spn_interrupts() {
-    if(spn1_hw_interrupt || spn2_hw_interrupt) {
+    asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
-        do{
+    while(spn1_hw_interrupt || spn2_hw_interrupt) {
-            asm("wfi");
+        asm volatile ("csrrs x0, mie, %0; wfi; nop" : : "r"(MIP_MEIP));
-            asm("nop");
+        asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
-        }while(spn1_hw_interrupt || spn2_hw_interrupt);
     }
     spn1_hw_interrupt=true;
     spn2_hw_interrupt=true;
+    set_csr(mie, MIP_MEIP);
 }
 
 /*!\brief initializes platform

raven_spn/src/raven_spn.cpp

@@ -14,8 +14,10 @@ void run_xspn1(int in_addr, int out_addr, int num_samples, int in_beats, int out
     spn_1::output_addr_reg() = out_addr;
     spn_1::num_of_in_beats_reg() = in_beats;  // Number of AXI4 burst beats needed to load all input data
     spn_1::num_of_out_beats_reg() = out_beats;    // Number of AXI4 burst beats needed to store all result data
-    spn_1::start_reg() = 1;
+    asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP)); // Disable interrupts
     printf("Starting first XSPN instance\n");
+    asm volatile ("csrrs x0, mie, %0; nop" : : "r"(MIP_MEIP)); // Enable interrupts
+    spn_1::start_reg() = 1;
 }
 
 void run_xspn2(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) {
@@ -25,7 +27,9 @@ void run_xspn2(int in_addr, int out_addr, int num_samples, int in_beats, int out
     spn_2::output_addr_reg() = out_addr;
     spn_2::num_of_in_beats_reg() = in_beats;  // Number of AXI4 burst beats needed to load all input data
     spn_2::num_of_out_beats_reg() = out_beats;    // Number of AXI4 burst beats needed to store all result data
+    asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP)); // Disable interrupts
     printf("Starting second XSPN instance\n");
+    asm volatile ("csrrs x0, mie, %0; nop" : : "r"(MIP_MEIP)); // Enable interrupts
     spn_2::start_reg() = 1;
 }