updates submodules and adapts to changes there

This commit is contained in:
Eyck Jentzsch 2023-12-17 12:24:55 +01:00
parent ac9aa90ff2
commit e279e8967e
5 changed files with 4 additions and 17 deletions

2
scc

@ -1 +1 @@
Subproject commit 7cf3d94c133b000e9dd5d29b5b7da670a15f0859 Subproject commit 1e7db7caf1117ec434b2d272a8556c6dded99b21

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@ -14,16 +14,7 @@ using namespace sysc::tgfs;
system::system(sc_core::sc_module_name nm) system::system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm) : sc_core::sc_module(nm)
, NAMED(router, platfrom_mmap.size() + 2, 2) , NAMED(router, platfrom_mmap.size() + 2, 2)
, NAMEDC(qspi0_ptr, spi, spi_impl::beh)
, NAMEDC(qspi1_ptr, spi, spi_impl::beh)
, NAMEDC(qspi2_ptr, spi, spi_impl::beh)
, qspi0(*qspi0_ptr)
, qspi1(*qspi1_ptr)
, qspi2(*qspi2_ptr)
{ {
auto& qspi0 = *qspi0_ptr;
auto& qspi1 = *qspi1_ptr;
auto& qspi2 = *qspi2_ptr;
core_complex.ibus(router.target[0]); core_complex.ibus(router.target[0]);
core_complex.dbus(router.target[1]); core_complex.dbus(router.target[1]);
size_t i = 0; size_t i = 0;

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@ -44,7 +44,7 @@ private:
scc::router<> router; scc::router<> router;
vpvper::sifive::uart_terminal uart0{"uart0"}; vpvper::sifive::uart_terminal uart0{"uart0"};
vpvper::sifive::uart uart1{"uart1"}; vpvper::sifive::uart uart1{"uart1"};
std::unique_ptr<vpvper::sifive::spi> qspi0_ptr, qspi1_ptr, qspi2_ptr; vpvper::sifive::spi qspi0{"qspi0"}, qspi1{"qspi1"}, qspi2{"qspi2"};
vpvper::sifive::pwm pwm0{"pwm0"}, pwm1{"pwm1"}, pwm2{"pwm2"}; vpvper::sifive::pwm pwm0{"pwm0"}, pwm1{"pwm1"}, pwm2{"pwm2"};
vpvper::sifive::gpio gpio0{"gpio0"}; vpvper::sifive::gpio gpio0{"gpio0"};
vpvper::sifive::plic plic{"plic"}; vpvper::sifive::plic plic{"plic"};
@ -65,11 +65,7 @@ private:
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> global_int_s{"global_int_s", 256}, local_int_s{"local_int_s", 16}; sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> global_int_s{"global_int_s", 256}, local_int_s{"local_int_s", 16};
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"}; sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> core_int_s{"core_int_s"};
protected:
void gen_reset(); void gen_reset();
vpvper::sifive::spi& qspi0;
vpvper::sifive::spi& qspi1;
vpvper::sifive::spi& qspi2;
#include "tgc_vp/gen/platform_mmap.h" #include "tgc_vp/gen/platform_mmap.h"
}; };

@ -1 +1 @@
Subproject commit bc4ea30815e77651ded4c51d97d7452c7ad005bb Subproject commit f4f90c5e65573d3bc979f447e3f78f794499d36e

2
vpvper

@ -1 +1 @@
Subproject commit 2df18a17549559131f52f9bcc90d3cef44aa4f5d Subproject commit 0b2dba5820ac06821306121f1d80b6b077fda4da