9 Commits

Include renames

Author	SHA1	Message	Date
eyck	6ee0cd1b29	update submodule pointers	2020-06-18 07:39:18 +02:00
eyck	255b379c20	Updated to latest versions	2019-07-14 16:51:43 +02:00
eyck	74601e280e	Merge branch 'master' of https://git.minres.com/VP/RISCV.git	2019-06-28 22:43:24 +02:00
eyck	679f311c52	Fixed clint interrupt method invokation	2019-06-28 20:59:16 +02:00
eyck	eb8365f4c3	Updated SC-Components	2019-04-11 05:40:02 +00:00
eyck	cb3a0d8411	Merge branch 'develop'	2019-01-10 11:15:02 +00:00
eyck	d5d236bf10	Adapted changes in SCC	2018-11-24 21:38:02 +01:00
eyck	20b3665003	Back-ported DVCon turorial changes	2018-11-12 19:36:44 +01:00
eyck	38099e3fc6	Added ADC, H-Bridge and motor models, refactored project structure	2018-07-28 09:45:49 +02:00