Commit Graph

17 Commits

Author SHA1 Message Date
Eyck Jentzsch ad1804d23e Updated to latest scc version 2020-01-09 19:40:19 +01:00
Eyck Jentzsch c199db7bfd Fixed C++11 compatibility 2019-07-16 15:54:15 +02:00
Eyck Jentzsch 255b379c20 Updated to latest versions 2019-07-14 16:51:43 +02:00
Eyck Jentzsch 74601e280e Merge branch 'master' of https://git.minres.com/VP/RISCV.git 2019-06-28 22:43:24 +02:00
Eyck Jentzsch 679f311c52 Fixed clint interrupt method invokation 2019-06-28 20:59:16 +02:00
Eyck Jentzsch 9ba1482fc2 Cleanup dependencies 2019-06-18 19:21:51 +00:00
Eyck Jentzsch aa6c308eaa Enhanced CLI parsing to allow non-option values 2019-06-15 20:23:01 +00:00
Eyck Jentzsch d2a9b1a744 Bumped SystemC version 2019-06-15 20:21:50 +00:00
Eyck Jentzsch 19da33fb20 Reorganized repo layout 2019-06-11 19:26:49 +00:00
Eyck Jentzsch eb8365f4c3 Updated SC-Components 2019-04-11 05:40:02 +00:00
Eyck Jentzsch cb3a0d8411 Merge branch 'develop' 2019-01-10 11:15:02 +00:00
eyck f69b529cab Fixed implementation of RV64 so that remaining riscv-test pass 2019-01-10 10:35:20 +00:00
Eyck Jentzsch d5d236bf10 Adapted changes in SCC 2018-11-24 21:38:02 +01:00
Eyck Jentzsch df03e90181 Adapted to vm_base refactoring (move into llvm package) 2018-11-22 20:28:36 +01:00
Eyck Jentzsch 58a446e6bc Refoctored to to move SystemC wrapper into riscv library 2018-11-19 20:39:11 +01:00
Eyck Jentzsch 20b3665003 Back-ported DVCon turorial changes 2018-11-12 19:36:44 +01:00
Eyck Jentzsch 38099e3fc6 Added ADC, H-Bridge and motor models, refactored project structure 2018-07-28 09:45:49 +02:00