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add SPI RTL representation

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This commit is contained in:
Eyck Jentzsch
2020-10-11 16:05:13 +02:00
parent 9248b7f246
commit 7a9802f68b
11 changed files with 5284 additions and 0 deletions
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21
platform/src/CMakeLists.txt
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@ -29,9 +29,24 @@ set(LIB_SOURCES
sysc/uart.cpp
CLIParser.cpp )
if(VERILATOR_FOUND)
set(LIB_SOURCES ${LIB_SOURCES}
rtl/spi_rtl.cpp
rtl/tl_uh_bfm.cpp
rtl/VTLSPI__Syms.cpp
rtl/VTLSPI.cpp
)
set_source_files_properties(beh/fe310.cpp PROPERTIES COMPILE_DEFINITIONS "HAS_VERILATOR")
endif()
add_library(platform ${LIB_SOURCES})
target_include_directories(platform PUBLIC ../incl)
target_link_libraries(platform PUBLIC riscv_sc CONAN_PKG::seasocks external)
if(VERILATOR_FOUND)
message(STATUS "Verilator found at ${VERILATOR_EXECUTABLE}")
target_include_directories(platform PRIVATE ${PROJECT_SOURCE_DIR}/incl/sysc/rtl)
target_include_directories(platform SYSTEM PRIVATE ${VERILATOR_INCLUDE_DIR})
endif()
set_target_properties(platform PROPERTIES
VERSION ${PROJECT_VERSION} # ${VERSION} was defined in the main CMakeLists.
FRAMEWORK FALSE
@ -42,6 +57,12 @@ add_executable(riscv-vp sc_main.cpp)
# include files for this application
target_include_directories(riscv-vp SYSTEM PRIVATE ${LLVM_INCLUDE_DIRS})
target_link_libraries(riscv-vp PUBLIC platform riscv_sc)
if(VERILATOR_FOUND)
set_source_files_properties(sc_main.cpp PROPERTIES COMPILE_DEFINITIONS HAS_VERILATOR)
target_include_directories(riscv-vp SYSTEM PRIVATE ${VERILATOR_INCLUDE_DIR})
target_link_libraries(riscv-vp verilated)
endif()
if (Tcmalloc_FOUND)
target_link_libraries(riscv-vp PUBLIC ${Tcmalloc_LIBRARIES})
endif(Tcmalloc_FOUND)

4364
platform/src/rtl/VTLSPI.cpp Normal file
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File diff suppressed because it is too large Load Diff

22
platform/src/rtl/VTLSPI__Syms.cpp Normal file
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@ -0,0 +1,22 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VTLSPI__Syms.h"
#include "VTLSPI.h"
// FUNCTIONS
VTLSPI__Syms::VTLSPI__Syms(VTLSPI *topp, const char *namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
// Setup scope names
__Vscope_TLSPI__TLMonitor.configure(this, name(), "TLSPI.TLMonitor");
__Vscope_TLSPI__buffer__TLMonitor.configure(this, name(), "TLSPI.buffer.TLMonitor");
}

214
platform/src/rtl/spi_rtl.cpp Normal file
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@ -0,0 +1,214 @@
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "scc/signal_initiator_mixin.h"
#include "scc/time2tick.h"
#include "sysc/SiFive/spi.h"
#include "sysc/rtl/tl_uh_bfm.h"
#include <VTLSPI.h>
#include <scc/utilities.h>
#include <tlm.h>
#include <tlm/tlm_signal_conv.h>
namespace sysc {
namespace spi_impl {
using namespace sc_core;
class rtl : public spi {
public:
SC_HAS_PROCESS(beh);// NOLINT
rtl(sc_module_name nm);
~rtl() override;
// void trace( sc_trace_file* tf ) const override {
// }
private:
sc_signal<bool> clock;
sc_signal<uint32_t> a_bits_address;
sc_signal<uint32_t> a_bits_data;
sc_signal<bool> a_ready;
sc_signal<bool> a_valid;
sc_signal<uint32_t> a_bits_opcode;
sc_signal<uint32_t> a_bits_param;
sc_signal<uint32_t> a_bits_size;
sc_signal<uint32_t> a_bits_source;
sc_signal<uint32_t> a_bits_mask;
sc_signal<bool> a_bits_corrupt;
sc_signal<uint32_t> d_bits_data;
sc_signal<bool> d_ready;
sc_signal<bool> d_valid;
sc_signal<uint32_t> d_bits_opcode;
sc_signal<uint32_t> d_bits_size;
sc_signal<uint32_t> d_bits_source;
sc_signal<bool> sck;
sc_signal<bool> dq_0_i;
sc_signal<bool> dq_0_o;
sc_signal<bool> dq_0_oe;
sc_signal<bool> dq_1_i;
sc_signal<bool> dq_1_o;
sc_signal<bool> dq_1_oe;
sc_signal<bool> dq_2_i;
sc_signal<bool> dq_3_i;
sc_signal<bool> cs_0;
sc_signal<bool> cs_2;
sc_signal<bool> cs_3;
VTLSPI i_vtlspi;
tl_uh_bfm i_tlbfm;
scc::time2tick i_time2tick;
tlm::sc_signal2tlm_signal<bool> i_sck_conv;
tlm::sc_signal2tlm_signal<bool> i_mosi_conv;
tlm::tlm_signal2sc_signal<bool> i_miso_conv;
tlm::sc_signal2tlm_signal<bool> i_scs0_conv, i_scs2_conv, i_scs3_conv;
scc::tlm_signal_bool_opt_out scs_1;
};
rtl::rtl(sc_module_name nm)
: spi(nm)
, NAMED(a_bits_address)
, NAMED(a_bits_data)
, NAMED(a_ready)
, NAMED(a_valid)
, NAMED(a_bits_opcode)
, NAMED(a_bits_param)
, NAMED(a_bits_size)
, NAMED(a_bits_source)
, NAMED(a_bits_mask)
, NAMED(a_bits_corrupt)
, NAMED(d_bits_data)
, NAMED(d_ready)
, NAMED(d_valid)
, NAMED(d_bits_opcode)
, NAMED(d_bits_size)
, NAMED(d_bits_source)
, NAMED(sck)
, NAMED(dq_0_i)
, NAMED(dq_0_o)
, NAMED(dq_0_oe)
, NAMED(dq_1_i)
, NAMED(dq_1_o)
, NAMED(dq_1_oe)
, NAMED(dq_2_i)
, NAMED(dq_3_i)
, NAMED(cs_0)
, NAMED(cs_2)
, NAMED(cs_3)
, NAMED(i_vtlspi)
, NAMED(i_tlbfm, 0x10024000)
, NAMED(i_time2tick)
, NAMED(i_sck_conv)
, NAMED(i_mosi_conv)
, NAMED(i_miso_conv)
, NAMED(i_scs0_conv)
, NAMED(i_scs2_conv)
, NAMED(i_scs3_conv)
, NAMED(scs_1) {
i_vtlspi.clock(clock);
i_vtlspi.reset(rst_i);
i_vtlspi.auto_int_xing_out_sync_0(irq_o);
i_vtlspi.auto_control_xing_in_a_ready(a_ready);
i_vtlspi.auto_control_xing_in_a_valid(a_valid);
i_vtlspi.auto_control_xing_in_a_bits_address(a_bits_address);
i_vtlspi.auto_control_xing_in_a_bits_data(a_bits_data);
i_vtlspi.auto_control_xing_in_a_bits_opcode(a_bits_opcode);
i_vtlspi.auto_control_xing_in_a_bits_param(a_bits_param);
i_vtlspi.auto_control_xing_in_a_bits_size(a_bits_size);
i_vtlspi.auto_control_xing_in_a_bits_source(a_bits_source);
i_vtlspi.auto_control_xing_in_a_bits_mask(a_bits_mask);
i_vtlspi.auto_control_xing_in_a_bits_corrupt(a_bits_corrupt);
i_vtlspi.auto_control_xing_in_d_ready(d_ready);
i_vtlspi.auto_control_xing_in_d_valid(d_valid);
i_vtlspi.auto_control_xing_in_d_bits_data(d_bits_data);
i_vtlspi.auto_control_xing_in_d_bits_opcode(d_bits_opcode);
i_vtlspi.auto_control_xing_in_d_bits_size(d_bits_size);
i_vtlspi.auto_control_xing_in_d_bits_source(d_bits_source);
i_vtlspi.auto_io_out_sck(sck);
i_vtlspi.auto_io_out_dq_0_i(dq_0_i);
i_vtlspi.auto_io_out_dq_0_o(dq_0_o);
i_vtlspi.auto_io_out_dq_0_oe(dq_0_oe);
i_vtlspi.auto_io_out_dq_1_i(dq_1_i);
i_vtlspi.auto_io_out_dq_1_o(dq_1_o);
i_vtlspi.auto_io_out_dq_1_oe(dq_1_oe);
i_vtlspi.auto_io_out_dq_2_i(dq_2_i);
i_vtlspi.auto_io_out_dq_3_i(dq_3_i);
i_vtlspi.auto_io_out_cs_0(cs_0);
i_vtlspi.auto_io_out_cs_2(cs_2);
i_vtlspi.auto_io_out_cs_3(cs_3);
i_tlbfm.clock(clock);
i_tlbfm.reset(rst_i);
spi::socket(i_tlbfm.socket);
i_tlbfm.a_ready(a_ready);
i_tlbfm.a_valid(a_valid);
i_tlbfm.a_bits_address(a_bits_address);
i_tlbfm.a_bits_data(a_bits_data);
i_tlbfm.d_bits_data(d_bits_data);
i_tlbfm.a_bits_opcode(a_bits_opcode);
i_tlbfm.a_bits_param(a_bits_param);
i_tlbfm.a_bits_size(a_bits_size);
i_tlbfm.a_bits_source(a_bits_source);
i_tlbfm.a_bits_mask(a_bits_mask);
i_tlbfm.a_bits_corrupt(a_bits_corrupt);
i_tlbfm.d_ready(d_ready);
i_tlbfm.d_valid(d_valid);
i_tlbfm.d_bits_opcode(d_bits_opcode);
i_tlbfm.d_bits_size(d_bits_size);
i_tlbfm.d_bits_source(d_bits_source);
i_time2tick.clk_i(clk_i);
i_time2tick.clk_o(clock);
i_sck_conv.s_i(sck);
i_sck_conv.t_o(sck_o);
i_mosi_conv.s_i(dq_0_o);
i_mosi_conv.t_o(mosi_o);
miso_i(i_miso_conv.t_i);
i_miso_conv.s_o(dq_0_i);
i_scs0_conv.s_i(cs_0);
i_scs0_conv.t_o(scs_o[0]);
i_scs2_conv.s_i(cs_2);
i_scs2_conv.t_o(scs_o[2]);
scs_1(scs_o[1]); // dummy to drive port
i_scs3_conv.s_i(cs_3);
i_scs3_conv.t_o(scs_o[3]);
}
rtl::~rtl() = default;
}
template <> std::unique_ptr<spi> spi::create<sysc::spi_impl::rtl>(sc_core::sc_module_name nm) {
auto *res = new sysc::spi_impl::rtl(nm);
return std::unique_ptr<spi>(res);
}
} /* namespace sysc */

142
platform/src/rtl/tl_uh_bfm.cpp Normal file
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@ -0,0 +1,142 @@
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/rtl/tl_uh_bfm.h"
#include <scc/report.h>
#include <scc/utilities.h>
namespace sysc {
using namespace sc_core;
tl_uh_bfm::tl_uh_bfm(sc_module_name nm, int64_t offset)
: sc_module(nm)
, offset(offset)
, NAMED(socket)
, NAMED(clock)
, NAMED(reset)
, NAMED(a_bits_address)
, NAMED(a_bits_data)
, NAMED(a_ready)
, NAMED(a_valid)
, NAMED(a_bits_opcode)
, NAMED(a_bits_param)
, NAMED(a_bits_size)
, NAMED(a_bits_source)
, NAMED(a_bits_mask)
, NAMED(a_bits_corrupt)
, NAMED(d_bits_data)
, NAMED(d_ready)
, NAMED(d_valid)
, NAMED(d_bits_opcode)
, NAMED(d_bits_size)
, NAMED(d_bits_source)
, NAMED(fw_queue) {
socket.register_nb_transport_fw(
[this](tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (phase == tlm::BEGIN_REQ && gp.get_command() != tlm::TLM_IGNORE_COMMAND) {
gp.acquire();
fw_queue.notify(gp, delay);
return tlm::TLM_ACCEPTED;
} else if (phase == tlm::END_RESP) {
gp.release();
d_ready = true;
}
});
SC_METHOD(tl_response_method);
sensitive << clock.pos();
SC_THREAD(fw_thread);
}
tl_uh_bfm::~tl_uh_bfm() = default;
void tl_uh_bfm::fw_thread() {
d_ready = true;
while (true) {
a_valid = false;
wait(fw_queue.get_event());
auto gp = fw_queue.get_next_transaction();
if (gp->get_data_length() == 4) {
auto addr = gp->get_address() + offset;
a_bits_address = addr;
a_valid = true;
a_bits_param = 0;
a_bits_size = 2; // 2^2 bytes
a_bits_source = 0x55;
a_bits_mask = 0xf;
a_bits_corrupt = false;
if (gp->get_command() == tlm::TLM_WRITE_COMMAND) {
a_bits_opcode = PutFullData;
a_bits_data = *(uint32_t *)gp->get_data_ptr();
} else {
a_bits_opcode = Get;
a_bits_data = 0;
}
tl_in_progress.push_back(gp);
do {
wait(clock.posedge_event());
} while (a_ready == false);
} else
SCCERR("tlbfm") << "Got transaction with unequal length";
}
}
void tl_uh_bfm::tl_response_method() {
if (d_valid && d_ready) {
// if(d_bits_source==0x55){ // this is ours
auto gp = tl_in_progress.front();
sc_assert(gp && "Got TL response without a request in queue");
tl_in_progress.pop_front();
if (gp->get_command() == tlm::TLM_WRITE_COMMAND) {
sc_assert(d_bits_opcode == AccessAck &&
"TL did not respond with AccessAck to write request");
} else {
sc_assert(d_bits_opcode == AccessAckData &&
"TL did not respond with AccessAckData to read request");
*(uint32_t *)(gp->get_data_ptr()) = d_bits_data;
}
gp->set_response_status(tlm::TLM_OK_RESPONSE);
sc_core::sc_time delay;
tlm::tlm_phase phase{tlm::BEGIN_RESP};
auto ret = socket->nb_transport_bw(*gp, phase, delay);
if (ret == tlm::TLM_COMPLETED || (ret == tlm::TLM_UPDATED && phase == tlm::END_RESP)) {
d_ready = true;
gp->release();
} else
d_ready = false;
// }
}
}
} /* namespace sysc */

13
platform/src/sc_main.cpp
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@ -50,6 +50,15 @@
#endif
#include <fstream>
#include <sstream>
#ifdef HAS_VERILATOR
#include <verilated.h>
inline void configure_verilator() {
Verilated::commandArgs(sc_core::sc_argc(), const_cast<char **>(sc_core::sc_argv()));
}
#else
inline void configure_verilator() {}
#endif
const std::string core_path{"i_system.i_hifive1.i_fe310.i_core_complex"};
using namespace sc_core;
using namespace sysc;
@ -67,6 +76,10 @@ int sc_main(int argc, char *argv[]) {
///////////////////////////////////////////////////////////////////////////
sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING);
///////////////////////////////////////////////////////////////////////////
// Setup verilator infrastructure (if used)
///////////////////////////////////////////////////////////////////////////
configure_verilator();
///////////////////////////////////////////////////////////////////////////
// CLI argument parsing & logging setup
///////////////////////////////////////////////////////////////////////////
CLIParser parser(argc, argv);

6
platform/src/sysc/hifive1.cpp
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@ -89,21 +89,27 @@ BOOST_PP_REPEAT(8, PORT_NAMING, _)
// proxy callbacks
h_bridge[0].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
ha_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[1].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
la_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[2].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hb_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[3].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lb_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[4].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hc_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[5].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lc_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});