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Merge branch 'master' of https://git.minres.com/VP/RISCV.git

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This commit is contained in:
Eyck Jentzsch
2019-06-28 22:43:17 +02:00
parent a2b49dd66c cb3a0d8411
commit 74601e280e
4 changed files with 7 additions and 3 deletions
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2
dbt-core

Submodule dbt-core updated: a9d808088e...dd900f0105

2
external/elfio vendored

Submodule external/elfio updated: 1fdbb64235...580da2467b

4
platform/src/sysc/plic.cpp
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@@ -50,7 +50,11 @@ plic::plic(sc_core::sc_module_name nm)
{ {
regs->registerResources(*this); regs->registerResources(*this);
// register callbacks // register callbacks
<<<<<<< HEAD
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool { regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
=======
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, uint32_t v, sc_core::sc_time d) -> bool {
>>>>>>> branch 'master' of https://git.minres.com/VP/RISCV.git
reg.put(v); reg.put(v);
reset_pending_int(v); reset_pending_int(v);
// std::cout << "Value of register: 0x" << std::hex << reg << std::endl; // std::cout << "Value of register: 0x" << std::hex << reg << std::endl;

2
scc

Submodule scc updated: 19a0c10fc2...2fd0f2c07f