Updated to latest versions
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319240ebcd
commit
255b379c20
2
dbt-core
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dbt-core
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Subproject commit dd900f0105655e8a592536b0a9ce494e1ab24263
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Subproject commit 87ecbd4ae12a3a1adc24dd1d5cfee4889b1b5866
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@ -50,11 +50,7 @@ plic::plic(sc_core::sc_module_name nm)
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{
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regs->registerResources(*this);
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// register callbacks
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<<<<<<< HEAD
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
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=======
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, uint32_t v, sc_core::sc_time d) -> bool {
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>>>>>>> branch 'master' of https://git.minres.com/VP/RISCV.git
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t v, sc_core::sc_time d) -> bool {
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reg.put(v);
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reset_pending_int(v);
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// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
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2
riscv
2
riscv
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Subproject commit e999d95623ceec1f6bc9e26f4d5f36e5d77b0bb8
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Subproject commit 1947a2114f82498f8a2f5c2af7690d482f1e55a3
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2
scc
2
scc
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Subproject commit 2fd0f2c07fd5323412397185b9507f19c32ef501
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Subproject commit 6558b1815baa8192f2dc6786611c76653272c136
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