VP/HIFIVE1-VP
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Updated to latest versions

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This commit is contained in:
Eyck Jentzsch
2019-07-14 16:51:43 +02:00
parent 319240ebcd
commit 255b379c20
4 changed files with 4 additions and 8 deletions
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2
dbt-core

Submodule dbt-core updated: dd900f0105...87ecbd4ae1

6
platform/src/sysc/plic.cpp
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@@ -50,11 +50,7 @@ plic::plic(sc_core::sc_module_name nm)
{ {
regs->registerResources(*this); regs->registerResources(*this);
// register callbacks // register callbacks
<<<<<<< HEAD regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t v, sc_core::sc_time d) -> bool {
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
=======
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, uint32_t v, sc_core::sc_time d) -> bool {
>>>>>>> branch 'master' of https://git.minres.com/VP/RISCV.git
reg.put(v); reg.put(v);
reset_pending_int(v); reset_pending_int(v);
// std::cout << "Value of register: 0x" << std::hex << reg << std::endl; // std::cout << "Value of register: 0x" << std::hex << reg << std::endl;

2
riscv

Submodule riscv updated: e999d95623...1947a2114f

2
scc

Submodule scc updated: 2fd0f2c07f...6558b1815b