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Code Issues 1 Packages Releases Wiki Activity

update target platform incl. XText/Xtend

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This commit is contained in:
Eyck Jentzsch
2022-02-13 12:40:21 +01:00
parent 564977ed54
commit c827f261ff
41 changed files with 1310 additions and 651 deletions
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8
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/GenerateRDL.mwe2
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@ -30,6 +30,7 @@ Workflow {
encoding = "UTF-8"
lineDelimiter = "\n"
fileHeader = "/*\n * generated by Xtext \${version}\n */"
preferXtendStubs = false
}
}
language = StandardLanguage {
@ -53,8 +54,10 @@ Workflow {
}
validator = {
// composedCheck = "org.eclipse.xtext.validation.NamesAreUniqueValidator"
composedCheck = "org.eclipse.xtext.validation.ImportUriValidator"
// composedCheck = "org.eclipse.xtext.validation.NamesAreUniqueValidator"
// Generates checks for @Deprecated grammar annotations, an IssueProvider and a corresponding PropertyPage
generateDeprecationValidation = true
}
generator = {
@ -64,6 +67,9 @@ Workflow {
projectWizard = {
generate = true
}
junitSupport = {
junitVersion = "5"
}
}
}
}

42
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/RdlUtil.xtend
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@ -11,6 +11,7 @@ import com.minres.rdl.rdl.PropertyAssignmentRhs
import com.minres.rdl.rdl.RValue
import com.minres.rdl.rdl.RValueConstant
import com.minres.rdl.rdl.InstancePropertyRef
import com.minres.rdl.rdl.Range
class RdlUtil {
@ -153,5 +154,44 @@ class RdlUtil {
componentSize = subInstantiation.byteSize(componentSize)
return componentSize
}
static def ComponentDefinition getComponentDefinition(Instantiation instantiation) {
if(instantiation.component!==null) instantiation.component else instantiation.componentRef
}
static def long absSize(Range range){
if(range.size!==null)
return (range.size as IntegerWithRadix).value
else
return Math.abs((range.left as IntegerWithRadix).value - (range.right as IntegerWithRadix).value)+1
}
static def boolean isFilledByField(Instantiation instantiation){
val fieldCount = instantiation.componentDefinition.instanceCountOfType(ComponentDefinitionType.FIELD)
if(fieldCount==1) {
val instSize=instantiation.size
val field = instantiation.component.instantiationsOfType(ComponentDefinitionType.FIELD).get(0)
val inst = field.componentInstances.get(0)
val range = inst.range
if(range===null)
return instSize==field.size
if(range.size !== null)
return instSize==(range.size as IntegerWithRadix).value
else {
val left=(range.left as IntegerWithRadix).value
val right=(range.right as IntegerWithRadix).value
val size = if(left>right) left-right+1 else right-left+1
return instSize==size
}
}
return false
}
static def int instanceCountOfType(ComponentDefinition definition, ComponentDefinitionType type){
val insts = definition.instantiationsOfType(type)
if(insts.size>0) {
insts.map[it.componentInstances.size].reduce[p1, p2| p1+p2]
} else
0
}
}

12
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/AddrmapGenerator.xtend
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@ -13,14 +13,18 @@ class AddrmapGenerator extends RdlBaseGenerator {
componentDefinition=definition
}
override generateHeader() {'''
override boolean getOverwrite(){
true
}
override generateHeader(String namespace) {'''
#ifndef _«componentDefinition.effectiveName.toUpperCase»_MAP_H_
#define _«componentDefinition.effectiveName.toUpperCase»_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, «componentDefinition.instanceCount(ComponentDefinitionType.REGFILE)»> «componentDefinition.effectiveName»_map = {{
const std::array<scc::target_memory_map_entry<32>, «componentDefinition.instanceCount(ComponentDefinitionType.REGFILE)»> «componentDefinition.effectiveName»_map = {{
«FOR instantiation : componentDefinition.instantiationsOfType(ComponentDefinitionType.REGFILE)»
«FOR instance : instantiation.componentInstances»
{&i_«instance.name», «instance.addressValue», 0x«Long.toHexString(instantiation.byteSize)»},
{i_«instance.name».socket, «instance.addressValue», 0x«Long.toHexString(instantiation.byteSize)»},
«ENDFOR»
«ENDFOR»
}};
@ -29,7 +33,7 @@ class AddrmapGenerator extends RdlBaseGenerator {
'''
}
override generateSource() {
override generateSource(String namespace) {
''
}

14
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwAddrmapGenerator.xtend
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@ -16,9 +16,13 @@ class FwAddrmapGenerator extends RdlBaseGenerator {
val nameMap = newLinkedHashSet()
override generateHeader() {'''
override boolean getOverwrite(){
true
}
override generateHeader(String namespace) {'''
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2020, MINRES Technologies GmbH
// Copyright (C) 2020-2022, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@ -57,10 +61,10 @@ class FwAddrmapGenerator extends RdlBaseGenerator {
«FOR instantiation : componentDefinition.instantiationsOfType(ComponentDefinitionType.REGFILE)»
«IF instantiation.component !== null && !nameMap.contains(instantiation.component.name)»
#include "«instantiation.component.name».h"«nameMap.add(instantiation.component.name)»
#include "«instantiation.component.name».h"«nameMap.add(instantiation.component.name)?"":""»
«ENDIF»
«IF instantiation.componentRef !== null && !nameMap.contains(instantiation.componentRef.name)»
#include "«instantiation.componentRef.name».h"«nameMap.add(instantiation.componentRef.name)»
#include "«instantiation.componentRef.name».h"«nameMap.add(instantiation.componentRef.name)?"":""»
«ENDIF»
«ENDFOR»
@ -80,7 +84,7 @@ class FwAddrmapGenerator extends RdlBaseGenerator {
'''
}
override generateSource() {
override generateSource(String namespace) {
''
}
}

45
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwRegfileGenerator.xtend
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@ -6,7 +6,6 @@ import com.minres.rdl.rdl.ComponentDefinitionType
import com.minres.rdl.rdl.ComponentInstance
import com.minres.rdl.rdl.Instantiation
import java.util.Date
import com.minres.rdl.rdl.Range
import static extension com.minres.rdl.RdlUtil.*
@ -18,9 +17,13 @@ class FwRegfileGenerator extends RdlBaseGenerator{
componentDefinition=definition
}
override String generateHeader()'''
override boolean getOverwrite(){
true
}
override String generateHeader(String namespace)'''
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2020, MINRES Technologies GmbH
// Copyright (C) 2020-2022, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@ -117,40 +120,8 @@ class FwRegfileGenerator extends RdlBaseGenerator{
#endif // _«componentDefinition.name.toUpperCase»_H_
'''
def long absSize(Range range){
if(range.size!==null)
return (range.size as IntegerWithRadix).value
else
return Math.abs((range.left as IntegerWithRadix).value - (range.right as IntegerWithRadix).value)+1
}
def boolean isFilledByField(Instantiation instantiation){
val fieldCount = instantiation.component.instanceCountOfType(ComponentDefinitionType.FIELD)
if(fieldCount==1) {
val instSize=instantiation.size
val field = instantiation.component.instantiationsOfType(ComponentDefinitionType.FIELD).get(0)
val inst = field.componentInstances.get(0)
val range = inst.range
if(range===null)
return instSize==field.size
if(range.size !== null)
return instSize==(range.size as IntegerWithRadix).value
else {
val left=(range.left as IntegerWithRadix).value
val right=(range.right as IntegerWithRadix).value
val size = if(left>right) left-right+1 else right-left+1
return instSize==size
}
}
return false
}
def int instanceCountOfType(ComponentDefinition definition, ComponentDefinitionType type){
definition.instantiationsOfType(type).map[it.componentInstances.size].reduce[p1, p2|p1+p1]
}
override generateSource() {
override generateSource(String namespace) {
''
}

9
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/Main.xtend
View File

@ -23,7 +23,7 @@ import org.eclipse.xtext.generator.IFileSystemAccess
class Main {
val USAGE_STR = "RDL2code [-h] [-v] [-I <RDL include dir] [-o <output dir>] <input file> <input file>";
val USAGE_STR = "RDL2code [-h] [-v] [-f] [-n <namespace>] [-I <RDL include dir] [-o <output dir>] <input file> <input file>";
def static main(String[] args) {
if (args.empty) {
@ -60,6 +60,8 @@ class Main {
val opt = new Options(args, 0, Integer.MAX_VALUE);
opt.getSet().addOption("h", Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("v", Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("f", Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("n", Separator.BLANK, Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("o", Separator.BLANK, Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("I", Separator.BLANK, Multiplicity.ZERO_OR_ONE);
if (!opt.check(false, false)) { // Print usage hints
@ -106,7 +108,10 @@ class Main {
throw new ParseException("error validating " + resource.URI, issues.size)
}
val context = new GeneratorContext => [cancelIndicator = CancelIndicator.NullImpl]
val context = new RdlGeneratorContext => [cancelIndicator = CancelIndicator.NullImpl]
context.forceOverwrite= opt.getSet().isSet('f')
if(opt.getSet().isSet('n'))
context.namespace=opt.getSet().getOption('n').getResultValue(0)
generator.generate(resource, fileAccess, context)
if(verbose) println('Code generation for ' + string + ' finished')

107
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/ModuleGenerator.xtend Normal file
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@ -0,0 +1,107 @@
package com.minres.rdl.generator
import com.minres.rdl.rdl.ComponentDefinition
import com.minres.rdl.rdl.ComponentDefinitionType
import static extension com.minres.rdl.RdlUtil.*
class ModuleGenerator extends RdlBaseGenerator {
val ComponentDefinition componentDefinition
new(ComponentDefinition definition) {
componentDefinition=definition
}
override boolean getOverwrite(){
false
}
override generateHeader(String namespace){
if(componentDefinition.type!=ComponentDefinitionType.REGFILE) return ''
val addrMaps = componentDefinition.eResource.resourceSet.allContents
.filter[ it instanceof ComponentDefinition]
.map[it as ComponentDefinition]
.filter[it.type == ComponentDefinitionType.ADDRMAP]
.filter[def | def.instantiations.filter[it.componentRef==componentDefinition].size>0]
if(addrMaps.size==0) return ''
'''
#ifndef _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_
#define _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_
#include <scc/tlm_target.h>
namespace «namespace» {
namespace gen {
class «componentDefinition.effectiveName»_regs;
}
class «componentDefinition.effectiveName» : public sc_core::sc_module, public scc::tlm_target<> {
public:
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
sc_core::sc_in<bool> rst_i{"rst_i"};
«componentDefinition.effectiveName»(sc_core::sc_module_name nm);
virtual ~«componentDefinition.effectiveName»() override;
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<gen::«componentDefinition.effectiveName»_regs> regs;
};
} /* namespace «namespace» */
#endif /* _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_ */
'''
}
override generateSource(String namespace) {
if(componentDefinition.type!=ComponentDefinitionType.REGFILE) return ''
val addrMaps = componentDefinition.eResource.resourceSet.allContents
.filter[ it instanceof ComponentDefinition]
.map[it as ComponentDefinition]
.filter[it.type == ComponentDefinitionType.ADDRMAP]
.filter[def | def.instantiations.filter[it.componentRef==componentDefinition].size>0]
if(addrMaps.size==0) return ''
'''
/*
* Copyright (c) 2019 -2022 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "«componentDefinition.effectiveName».h"
#include "gen/«componentDefinition.effectiveName».h"
#include <scc/utilities.h>
namespace «namespace» {
SC_HAS_PROCESS(«componentDefinition.effectiveName»);// NOLINT
«componentDefinition.effectiveName»::«componentDefinition.effectiveName»(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, scc::tlm_target<>(clk)
, NAMEDD(regs, gen::«componentDefinition.effectiveName»_regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;
SC_METHOD(reset_cb);
sensitive << rst_i;
}
«componentDefinition.effectiveName»::~«componentDefinition.effectiveName»() {} // NOLINT
void «componentDefinition.effectiveName»::clock_cb() { this->clk = clk_i.read(); }
void «componentDefinition.effectiveName»::reset_cb() {
if (rst_i.read()) {
regs->reset_start();
} else {
regs->reset_stop();
}
}
} /* namespace «namespace» */
'''
}
}

30
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RDLGenerator.xtend
View File

@ -18,25 +18,35 @@ import java.util.Map
* See https://www.eclipse.org/Xtext/documentation/303_runtime_concepts.html#code-generation
*/
class RDLGenerator extends AbstractGenerator {
override void doGenerate(Resource resource, IFileSystemAccess2 fsa, IGeneratorContext context) {
val force = if(context instanceof RdlGeneratorContext) context.forceOverwrite else false
val namespace = if(context instanceof RdlGeneratorContext) context.namespace else "sysc"
resource.resourceSet.allContents.filter[ it instanceof ComponentDefinition].map[it as ComponentDefinition].forEach[
val genMap = it.fileGenerator
if(genMap!==null) genMap.forEach[p1, gen |
val header = gen.generateHeader
if(header!==null && header.length>0)
fsa.generateFile(p1+'/'+it.effectiveName+'.h', fsa.outputConfig('incl-out'), header)
val source = gen.generateSource
if(source!==null && source.length>0)
fsa.generateFile(p1+'/'+it.effectiveName+'.cpp', fsa.outputConfig('src-out'), source)
val header = gen.generateHeader(namespace)
val inclFileName = p1+'/'+it.effectiveName+'.h'
val inclCfg = fsa.outputConfig('incl-out')
if((force || !fsa.isFile(inclFileName, inclCfg) || gen.overwrite) && header!==null && header.length>0)
fsa.generateFile(inclFileName, inclCfg, header)
val source = gen.generateSource(namespace)
val srcFileName = p1+'/'+it.effectiveName+'.cpp'
val srcCfg = fsa.outputConfig('src-out')
if((force || !fsa.isFile(srcFileName, srcCfg) || gen.overwrite) && source!==null && source.length>0)
fsa.generateFile(srcFileName, srcCfg, source)
]
]
}
def Map<String, RdlBaseGenerator> fileGenerator(ComponentDefinition definition){
switch(definition.type){
case ComponentDefinitionType.REGFILE: #{'vp' -> new RegfileGenerator(definition), 'fw' -> new FwRegfileGenerator(definition)}
case ComponentDefinitionType.ADDRMAP: #{'vp' -> new AddrmapGenerator(definition), 'fw' -> new FwAddrmapGenerator(definition)}
case ComponentDefinitionType.REGFILE: #{
'gen' -> new RegfileGenerator(definition),
'fw' -> new FwRegfileGenerator(definition),
'.' -> new ModuleGenerator(definition)}
case ComponentDefinitionType.ADDRMAP: #{
'gen' -> new AddrmapGenerator(definition),
'fw' -> new FwAddrmapGenerator(definition)}
default: null
}
}

6
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlBaseGenerator.xtend
View File

@ -2,8 +2,10 @@ package com.minres.rdl.generator
abstract class RdlBaseGenerator {
def String generateHeader()
def String generateHeader(String namespace)
def String generateSource()
def String generateSource(String namespace)
def boolean getOverwrite()
}

8
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlGeneratorContext.xtend Normal file
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@ -0,0 +1,8 @@
package com.minres.rdl.generator
import org.eclipse.xtext.generator.GeneratorContext
class RdlGeneratorContext extends GeneratorContext {
public boolean forceOverwrite = false
public String namespace ="scc"
}

149
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RegfileGenerator.xtend
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@ -6,7 +6,6 @@ import com.minres.rdl.rdl.ComponentDefinitionType
import com.minres.rdl.rdl.ComponentInstance
import com.minres.rdl.rdl.Instantiation
import java.util.Date
import com.minres.rdl.rdl.Range
import static extension com.minres.rdl.RdlUtil.*
@ -18,9 +17,13 @@ class RegfileGenerator extends RdlBaseGenerator{
componentDefinition=definition
}
override String generateHeader()'''
override boolean getOverwrite(){
true
}
override String generateHeader(String namespace)'''
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// Copyright (C) 2017-2022, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@ -50,26 +53,34 @@ class RegfileGenerator extends RdlBaseGenerator{
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: «new Date»
// * «componentDefinition.name».h Author: <RDL Generator>
// * «componentDefinition.effectiveName».h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _«componentDefinition.name.toUpperCase»_H_
#define _«componentDefinition.name.toUpperCase»_H_
#ifndef _«namespace.toUpperCase»_GEN_«componentDefinition.effectiveName.toUpperCase»_H_
#define _«namespace.toUpperCase»_GEN_«componentDefinition.effectiveName.toUpperCase»_H_
#include <sysc/utilities.h>
#include <scc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <scc/register.h>
#include <scc/tlm_target.h>
«FOR instantiation : componentDefinition.instantiations»
«IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
#include "«instantiation.componentDefinition.effectiveName».h"
«ENDIF»
«ENDFOR»
namespace sysc {
namespace «namespace» {
namespace gen {
class «componentDefinition.name» :
class «componentDefinition.effectiveName»_regs :
public sc_core::sc_module,
public sysc::resetable
public scc::resetable
{
public:
//////////////////////////////////////////////////////////////////////////////
// storage declarations
//////////////////////////////////////////////////////////////////////////////
«FOR cdef : componentDefinition.componentDefinitions»
«IF cdef.type == ComponentDefinitionType.REG»
BEGIN_BF_DECL(«cdef.effectiveName»+'_t'», uint«cdef»_t);
@ -78,10 +89,11 @@ class RegfileGenerator extends RdlBaseGenerator{
«ENDIF»
«ENDFOR»
«FOR instantiation : componentDefinition.instantiations»
«IF instantiation.componentRef !==null && instantiation.componentRef.type == ComponentDefinitionType.REG»
«instantiation.componentRef.effectiveName»+'_t' «instantiation.componentInstances.map[it.name].join(', ')»;
«ENDIF»
«IF instantiation.component !== null && instantiation.component.type == ComponentDefinitionType.REG»
«IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
«FOR instance : instantiation.componentInstances»
«instantiation.componentDefinition.effectiveName»_regs i_«instance.name»{"«instance.name»"};
«ENDFOR»
«ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
«IF instantiation.isFilledByField»
«IF instantiation.componentInstances.filter[it.range===null].size>0»
uint«instantiation.size»_t «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
@ -89,8 +101,14 @@ class RegfileGenerator extends RdlBaseGenerator{
«FOR componentInstance : instantiation.componentInstances.filter[it.range!==null]»
std::array<uint«instantiation.size»_t, «componentInstance.range.absSize»> r_«componentInstance.name»;
«ENDFOR»
«ENDIF»
«IF !instantiation.isFilledByField»
«ELSEIF instantiation.componentDefinition.instantiations.size==0»
«IF instantiation.componentInstances.filter[it.range===null].size>0»
uint«instantiation.size»_t «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
«ENDIF»
«FOR componentInstance : instantiation.componentInstances.filter[it.range!==null]»
std::array<uint«instantiation.size»_t, «componentInstance.range.absSize»> r_«componentInstance.name»;
«ENDFOR»
«ELSE»
BEGIN_BF_DECL(«instantiation.component.effectiveName»_t, uint«instantiation.size»_t);
«instantiation.definingComponent.genFieldDeclarations»
END_BF_DECL() «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
@ -98,96 +116,79 @@ class RegfileGenerator extends RdlBaseGenerator{
std::array<«instantiation.component.effectiveName»_t, «componentInstance.range.absSize»> r_«componentInstance.name»;
«ENDFOR»
«ENDIF»
«ENDIF»
«ENDFOR»
//////////////////////////////////////////////////////////////////////////////
// register declarations
//////////////////////////////////////////////////////////////////////////////
«FOR instantiation : componentDefinition.instantiations»
«FOR instance : instantiation.componentInstances»
«IF instance.range===null»
«IF instantiation.isFilledByField»
sysc::sc_register<uint«instantiation.size»_t> «instance.name»;
«ENDIF»
«IF !instantiation.isFilledByField»
sysc::sc_register<«instantiation.component.effectiveName»_t> «instance.name»;
«ENDIF»
«ENDIF»
«IF instance.range!==null»
«IF instantiation.isFilledByField»
sysc::sc_register_indexed<uint«instantiation.size»_t, «instance.range.absSize»> «instance.name»;
«ENDIF»
«IF !instantiation.isFilledByField»
sysc::sc_register_indexed<«instantiation.component.effectiveName»_t, «instance.range.absSize»> «instance.name»;
«IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
// scc::sc_register_file<«instantiation.componentDefinition.effectiveName»_regs> «instance.name»;
«ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
«IF instance.range===null»
«IF instantiation.componentDefinition.instantiations.size==0»
scc::sc_register<uint«instantiation.size»_t> «instance.name»;
«ELSEIF instantiation.isFilledByField»
scc::sc_register<uint«instantiation.size»_t> «instance.name»;
«ELSE»
scc::sc_register<«instantiation.componentDefinition.effectiveName»_t> «instance.name»;
«ENDIF»
«ELSE»
«IF instantiation.componentDefinition.instantiations.size==0»
scc::sc_register_indexed<uint«instantiation.size»_t, «instance.range.absSize»> «instance.name»;
«ELSEIF instantiation.isFilledByField»
scc::sc_register_indexed<uint«instantiation.size»_t, «instance.range.absSize»> «instance.name»;
«ELSE»
scc::sc_register_indexed<«instantiation.component.effectiveName»_t, «instance.range.absSize»> «instance.name»;
«ENDIF»
«ENDIF»
«ENDIF»
«ENDFOR»
«ENDFOR»
«componentDefinition.name»(sc_core::sc_module_name nm);
«componentDefinition.effectiveName»_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
void registerResources(scc::tlm_target<BUSWIDTH>& target, uint64_t offset=0);
};
}
} // namespace gen
} // namespace «namespace»
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::«componentDefinition.name»::«componentDefinition.name»(sc_core::sc_module_name nm)
inline «namespace»::gen::«componentDefinition.effectiveName»_regs::«componentDefinition.effectiveName»_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
«FOR instantiation : componentDefinition.instantiations»
«FOR instance : instantiation.componentInstances»
, NAMED(«instance.name», r_«instance.name», 0, *this)
«IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
// , NAMED(«instance.name», i_«instance.name», 0, *this)
«ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
, NAMED(«instance.name», r_«instance.name», 0, *this)
«ENDIF»
«ENDFOR»
«ENDFOR»
{
}
template<unsigned BUSWIDTH>
inline void sysc::«componentDefinition.name»::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
inline void «namespace»::gen::«componentDefinition.effectiveName»_regs::registerResources(scc::tlm_target<BUSWIDTH>& target, uint64_t offset) {
«FOR instantiation : componentDefinition.instantiations»
«FOR instance : instantiation.componentInstances»
target.addResource(«instance.name», «instance.addressValue»UL);
«IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
i_«instance.name».registerResources(target, «instance.addressValue»UL+offset);
«ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
target.addResource(«instance.name», «instance.addressValue»UL);
«ENDIF»
«ENDFOR»
«ENDFOR»
}
#endif // _«componentDefinition.name.toUpperCase»_H_
#endif // _«namespace.toUpperCase»_GEN_«componentDefinition.effectiveName.toUpperCase»_H_
'''
def long absSize(Range range){
if(range.size!==null)
return (range.size as IntegerWithRadix).value
else
return Math.abs((range.left as IntegerWithRadix).value - (range.right as IntegerWithRadix).value)+1
}
def boolean isFilledByField(Instantiation instantiation){
val fieldCount = instantiation.component.instanceCountOfType(ComponentDefinitionType.FIELD)
if(fieldCount==1) {
val instSize=instantiation.size
val field = instantiation.component.instantiationsOfType(ComponentDefinitionType.FIELD).get(0)
val inst = field.componentInstances.get(0)
val range = inst.range
if(range===null)
return instSize==field.size
if(range.size !== null)
return instSize==(range.size as IntegerWithRadix).value
else {
val left=(range.left as IntegerWithRadix).value
val right=(range.right as IntegerWithRadix).value
val size = if(left>right) left-right+1 else right-left+1
return instSize==size
}
}
return false
}
def int instanceCountOfType(ComponentDefinition definition, ComponentDefinitionType type){
definition.instantiationsOfType(type).map[it.componentInstances.size].reduce[p1, p2|p1+p1]
}
override generateSource() {
override generateSource(String namespace) {
''
}