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Eyck Jentzsch 2017-09-13 10:42:46 +02:00
parent ae91be7619
commit 7c603c65f3
12 changed files with 3856 additions and 3800 deletions
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2
com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/contentassist/antlr/RDLParser.java
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@ -206,7 +206,7 @@ public class RDLParser extends AbstractContentAssistParser {
@Override
protected String[] getInitialHiddenTokens() {
return new String[] { "RULE_WS", "RULE_ML_COMMENT", "RULE_SL_COMMENT" };
return new String[] { "RULE_WS", "RULE_ML_COMMENT", "RULE_SL_COMMENT", "RULE_ESCAPE_JSP", "RULE_ESCAPE_ORDL" };
}
public RDLGrammarAccess getGrammarAccess() {

6
com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/contentassist/antlr/internal/InternalRDL.g
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@ -7643,10 +7643,14 @@ RULE_ID : '\\'? ('a'..'z'|'A'..'Z'|'_') ('a'..'z'|'A'..'Z'|'_'|'0'..'9')*;
RULE_WS : (' '|'\t'|'\r'|'\n')+;
RULE_ML_COMMENT : ('/*' ( options {greedy=false;} : . )*'*/'|'<%' ( options {greedy=false;} : . )*'%>'|'(' ( options {greedy=false;} : . )*')');
RULE_ML_COMMENT : '/*' ( options {greedy=false;} : . )*'*/';
RULE_SL_COMMENT : '//' ~(('\n'|'\r'))* ('\r'? '\n')?;
RULE_ESCAPE_JSP : '<%' ( options {greedy=false;} : . )*'%>';
RULE_ESCAPE_ORDL : '(' ( options {greedy=false;} : . )*')';
RULE_NUM : (('0'..'9')+ '\'b' ('0'|'1'|'_')+|('0'..'9')+ '\'o' ('0'..'7'|'_')+|('0'..'9')+ '\'h' ('0'..'9'|'a'..'f'|'A'..'F'|'_')+|('0'..'9')+ '\'d' ('0'..'9'|'_')+|'0x' ('0'..'9'|'a'..'f'|'A'..'F')+|('0'..'9')+);
RULE_STR : '"' ('\\' ('b'|'t'|'n'|'f'|'r'|'u'|'"'|'\''|'\\')|~(('\\'|'"')))* '"';

252
com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/contentassist/antlr/internal/InternalRDL.tokens
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@ -1,126 +1,128 @@
'%='=125
'+='=124
','=122
'->'=129
'.'=130
':'=128
';'=115
'='=117
'@'=123
'UNDEFINED'=95
'['=126
']'=127
'`include'=111
'accesswidth'=79
'activehigh'=58
'activelow'=59
'addressing'=82
'addrmap'=13
'alias'=121
'alignment'=75
'all'=19
'anded'=38
'arbiter'=22
'async'=55
'bigendian'=47
'boolean'=12
'bothedge'=108
'bridge'=50
'clock'=86
'compact'=103
'component'=119
'counter'=41
'cpuif_reset'=56
'decr'=63
'decrsaturate'=69
'decrthreshold'=71
'decrvalue'=67
'decrwidth'=65
'default'=118
'desc'=21
'dontcompare'=72
'donttest'=73
'enable'=88
'encode'=84
'enum'=131
'errextbus'=44
'external'=132
'false'=97
'field'=16
'field_reset'=57
'fieldwidth'=77
'fullalign'=105
'halt'=93
'haltenable'=92
'haltmask'=91
'hw'=81
'hwclr'=32
'hwenable'=89
'hwmask'=90
'hwset'=31
'incr'=62
'incrvalue'=66
'incrwidth'=64
'internal'=74
'intr'=37
'level'=109
'littleendian'=46
'lsb0'=53
'mask'=87
'msb0'=52
'na'=102
'name'=20
'negedge'=107
'next'=94
'nonsticky'=110
'number'=11
'ored'=39
'overflow'=42
'posedge'=106
'precedence'=83
'property'=112
'r'=100
'rclr'=24
'ref'=17
'reg'=14
'regalign'=104
'regfile'=15
'regwidth'=76
'reset'=45
'resetsignal'=85
'rset'=23
'rsvdset'=48
'rsvdsetX'=49
'rw'=98
'saturate'=68
'shared'=51
'sharedextbus'=43
'signal'=18
'signalwidth'=78
'singlepulse'=60
'sticky'=35
'stickybit'=36
'string'=10
'sw'=80
'swacc'=34
'swmod'=33
'swwe'=29
'swwel'=30
'sync'=54
'threshold'=70
'true'=96
'type'=116
'underflow'=61
'w'=101
'we'=27
'wel'=28
'woclr'=25
'woset'=26
'wr'=99
'xored'=40
'{'=113
'|'=120
'}'=114
'%='=127
'+='=126
','=124
'->'=131
'.'=132
':'=130
';'=117
'='=119
'@'=125
'UNDEFINED'=97
'['=128
']'=129
'`include'=113
'accesswidth'=81
'activehigh'=60
'activelow'=61
'addressing'=84
'addrmap'=15
'alias'=123
'alignment'=77
'all'=21
'anded'=40
'arbiter'=24
'async'=57
'bigendian'=49
'boolean'=14
'bothedge'=110
'bridge'=52
'clock'=88
'compact'=105
'component'=121
'counter'=43
'cpuif_reset'=58
'decr'=65
'decrsaturate'=71
'decrthreshold'=73
'decrvalue'=69
'decrwidth'=67
'default'=120
'desc'=23
'dontcompare'=74
'donttest'=75
'enable'=90
'encode'=86
'enum'=133
'errextbus'=46
'external'=134
'false'=99
'field'=18
'field_reset'=59
'fieldwidth'=79
'fullalign'=107
'halt'=95
'haltenable'=94
'haltmask'=93
'hw'=83
'hwclr'=34
'hwenable'=91
'hwmask'=92
'hwset'=33
'incr'=64
'incrvalue'=68
'incrwidth'=66
'internal'=76
'intr'=39
'level'=111
'littleendian'=48
'lsb0'=55
'mask'=89
'msb0'=54
'na'=104
'name'=22
'negedge'=109
'next'=96
'nonsticky'=112
'number'=13
'ored'=41
'overflow'=44
'posedge'=108
'precedence'=85
'property'=114
'r'=102
'rclr'=26
'ref'=19
'reg'=16
'regalign'=106
'regfile'=17
'regwidth'=78
'reset'=47
'resetsignal'=87
'rset'=25
'rsvdset'=50
'rsvdsetX'=51
'rw'=100
'saturate'=70
'shared'=53
'sharedextbus'=45
'signal'=20
'signalwidth'=80
'singlepulse'=62
'sticky'=37
'stickybit'=38
'string'=12
'sw'=82
'swacc'=36
'swmod'=35
'swwe'=31
'swwel'=32
'sync'=56
'threshold'=72
'true'=98
'type'=118
'underflow'=63
'w'=103
'we'=29
'wel'=30
'woclr'=27
'woset'=28
'wr'=101
'xored'=42
'{'=115
'|'=122
'}'=116
RULE_ESCAPE_JSP=10
RULE_ESCAPE_ORDL=11
RULE_ID=5
RULE_ML_COMMENT=8
RULE_NUM=6
@ -137,7 +139,6 @@ T__106=106
T__107=107
T__108=108
T__109=109
T__10=10
T__110=110
T__111=111
T__112=112
@ -148,7 +149,6 @@ T__116=116
T__117=117
T__118=118
T__119=119
T__11=11
T__120=120
T__121=121
T__122=122
@ -163,6 +163,8 @@ T__12=12
T__130=130
T__131=131
T__132=132
T__133=133
T__134=134
T__13=13
T__14=14
T__15=15

2701
com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/contentassist/antlr/internal/InternalRDLLexer.java
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File diff suppressed because it is too large Load Diff

870
com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/contentassist/antlr/internal/InternalRDLParser.java
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File diff suppressed because it is too large Load Diff

6
com.minres.rdl.parent/com.minres.rdl.ui/src-gen/com/minres/rdl/ui/contentassist/AbstractRDLProposalProvider.java
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@ -346,6 +346,12 @@ public abstract class AbstractRDLProposalProvider extends AbstractJavaBasedConte
public void complete_SL_COMMENT(EObject model, RuleCall ruleCall, ContentAssistContext context, ICompletionProposalAcceptor acceptor) {
// subclasses may override
}
public void complete_ESCAPE_JSP(EObject model, RuleCall ruleCall, ContentAssistContext context, ICompletionProposalAcceptor acceptor) {
// subclasses may override
}
public void complete_ESCAPE_ORDL(EObject model, RuleCall ruleCall, ContentAssistContext context, ICompletionProposalAcceptor acceptor) {
// subclasses may override
}
public void complete_NUM(EObject model, RuleCall ruleCall, ContentAssistContext context, ICompletionProposalAcceptor acceptor) {
// subclasses may override
}

2
com.minres.rdl.parent/com.minres.rdl/src-gen/com/minres/rdl/parser/antlr/RDLParser.java
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@ -16,7 +16,7 @@ public class RDLParser extends AbstractAntlrParser {
@Override
protected void setInitialHiddenTokens(XtextTokenStream tokenStream) {
tokenStream.setInitialHiddenTokens("RULE_WS", "RULE_ML_COMMENT", "RULE_SL_COMMENT");
tokenStream.setInitialHiddenTokens("RULE_WS", "RULE_ML_COMMENT", "RULE_SL_COMMENT", "RULE_ESCAPE_JSP", "RULE_ESCAPE_ORDL");
}

6
com.minres.rdl.parent/com.minres.rdl/src-gen/com/minres/rdl/parser/antlr/internal/InternalRDL.g
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@ -3576,10 +3576,14 @@ RULE_ID : '\\'? ('a'..'z'|'A'..'Z'|'_') ('a'..'z'|'A'..'Z'|'_'|'0'..'9')*;
RULE_WS : (' '|'\t'|'\r'|'\n')+;
RULE_ML_COMMENT : ('/*' ( options {greedy=false;} : . )*'*/'|'<%' ( options {greedy=false;} : . )*'%>'|'(' ( options {greedy=false;} : . )*')');
RULE_ML_COMMENT : '/*' ( options {greedy=false;} : . )*'*/';
RULE_SL_COMMENT : '//' ~(('\n'|'\r'))* ('\r'? '\n')?;
RULE_ESCAPE_JSP : '<%' ( options {greedy=false;} : . )*'%>';
RULE_ESCAPE_ORDL : '(' ( options {greedy=false;} : . )*')';
RULE_NUM : (('0'..'9')+ '\'b' ('0'|'1'|'_')+|('0'..'9')+ '\'o' ('0'..'7'|'_')+|('0'..'9')+ '\'h' ('0'..'9'|'a'..'f'|'A'..'F'|'_')+|('0'..'9')+ '\'d' ('0'..'9'|'_')+|'0x' ('0'..'9'|'a'..'f'|'A'..'F')+|('0'..'9')+);
RULE_STR : '"' ('\\' ('b'|'t'|'n'|'f'|'r'|'u'|'"'|'\''|'\\')|~(('\\'|'"')))* '"';

252
com.minres.rdl.parent/com.minres.rdl/src-gen/com/minres/rdl/parser/antlr/internal/InternalRDL.tokens
View File

@ -1,126 +1,128 @@
'%='=28
'+='=27
','=25
'->'=32
'.'=33
':'=30
';'=15
'='=14
'@'=26
'UNDEFINED'=119
'['=29
']'=31
'`include'=10
'accesswidth'=103
'activehigh'=83
'activelow'=84
'addressing'=106
'addrmap'=40
'alias'=24
'alignment'=99
'all'=46
'anded'=63
'arbiter'=47
'async'=80
'bigendian'=72
'boolean'=39
'bothedge'=130
'bridge'=75
'clock'=110
'compact'=125
'component'=20
'counter'=66
'cpuif_reset'=81
'decr'=88
'decrsaturate'=94
'decrthreshold'=96
'decrvalue'=92
'decrwidth'=90
'default'=17
'desc'=36
'dontcompare'=97
'donttest'=98
'enable'=112
'encode'=108
'enum'=34
'errextbus'=69
'external'=22
'false'=19
'field'=43
'field_reset'=82
'fieldwidth'=101
'fullalign'=127
'halt'=117
'haltenable'=116
'haltmask'=115
'hw'=105
'hwclr'=57
'hwenable'=113
'hwmask'=114
'hwset'=56
'incr'=87
'incrvalue'=91
'incrwidth'=89
'internal'=23
'intr'=62
'level'=131
'littleendian'=71
'lsb0'=78
'mask'=111
'msb0'=77
'na'=124
'name'=35
'negedge'=129
'next'=118
'nonsticky'=132
'number'=38
'ored'=64
'overflow'=67
'posedge'=128
'precedence'=107
'property'=11
'r'=122
'rclr'=49
'ref'=44
'reg'=41
'regalign'=126
'regfile'=42
'regwidth'=100
'reset'=70
'resetsignal'=109
'rset'=48
'rsvdset'=73
'rsvdsetX'=74
'rw'=120
'saturate'=93
'shared'=76
'sharedextbus'=68
'signal'=45
'signalwidth'=102
'singlepulse'=85
'sticky'=60
'stickybit'=61
'string'=37
'sw'=104
'swacc'=59
'swmod'=58
'swwe'=54
'swwel'=55
'sync'=79
'threshold'=95
'true'=18
'type'=13
'underflow'=86
'w'=123
'we'=52
'wel'=53
'woclr'=50
'woset'=51
'wr'=121
'xored'=65
'{'=12
'|'=21
'}'=16
'%='=30
'+='=29
','=27
'->'=34
'.'=35
':'=32
';'=17
'='=16
'@'=28
'UNDEFINED'=121
'['=31
']'=33
'`include'=12
'accesswidth'=105
'activehigh'=85
'activelow'=86
'addressing'=108
'addrmap'=42
'alias'=26
'alignment'=101
'all'=48
'anded'=65
'arbiter'=49
'async'=82
'bigendian'=74
'boolean'=41
'bothedge'=132
'bridge'=77
'clock'=112
'compact'=127
'component'=22
'counter'=68
'cpuif_reset'=83
'decr'=90
'decrsaturate'=96
'decrthreshold'=98
'decrvalue'=94
'decrwidth'=92
'default'=19
'desc'=38
'dontcompare'=99
'donttest'=100
'enable'=114
'encode'=110
'enum'=36
'errextbus'=71
'external'=24
'false'=21
'field'=45
'field_reset'=84
'fieldwidth'=103
'fullalign'=129
'halt'=119
'haltenable'=118
'haltmask'=117
'hw'=107
'hwclr'=59
'hwenable'=115
'hwmask'=116
'hwset'=58
'incr'=89
'incrvalue'=93
'incrwidth'=91
'internal'=25
'intr'=64
'level'=133
'littleendian'=73
'lsb0'=80
'mask'=113
'msb0'=79
'na'=126
'name'=37
'negedge'=131
'next'=120
'nonsticky'=134
'number'=40
'ored'=66
'overflow'=69
'posedge'=130
'precedence'=109
'property'=13
'r'=124
'rclr'=51
'ref'=46
'reg'=43
'regalign'=128
'regfile'=44
'regwidth'=102
'reset'=72
'resetsignal'=111
'rset'=50
'rsvdset'=75
'rsvdsetX'=76
'rw'=122
'saturate'=95
'shared'=78
'sharedextbus'=70
'signal'=47
'signalwidth'=104
'singlepulse'=87
'sticky'=62
'stickybit'=63
'string'=39
'sw'=106
'swacc'=61
'swmod'=60
'swwe'=56
'swwel'=57
'sync'=81
'threshold'=97
'true'=20
'type'=15
'underflow'=88
'w'=125
'we'=54
'wel'=55
'woclr'=52
'woset'=53
'wr'=123
'xored'=67
'{'=14
'|'=23
'}'=18
RULE_ESCAPE_JSP=10
RULE_ESCAPE_ORDL=11
RULE_ID=5
RULE_ML_COMMENT=8
RULE_NUM=6
@ -137,7 +139,6 @@ T__106=106
T__107=107
T__108=108
T__109=109
T__10=10
T__110=110
T__111=111
T__112=112
@ -148,7 +149,6 @@ T__116=116
T__117=117
T__118=118
T__119=119
T__11=11
T__120=120
T__121=121
T__122=122
@ -163,6 +163,8 @@ T__12=12
T__130=130
T__131=131
T__132=132
T__133=133
T__134=134
T__13=13
T__14=14
T__15=15

2681
com.minres.rdl.parent/com.minres.rdl/src-gen/com/minres/rdl/parser/antlr/internal/InternalRDLLexer.java
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860
com.minres.rdl.parent/com.minres.rdl/src-gen/com/minres/rdl/parser/antlr/internal/InternalRDLParser.java
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18
com.minres.rdl.parent/com.minres.rdl/src-gen/com/minres/rdl/services/RDLGrammarAccess.java
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@ -3381,6 +3381,8 @@ public class RDLGrammarAccess extends AbstractGrammarElementFinder {
private final TerminalRule tWS;
private final TerminalRule tML_COMMENT;
private final TerminalRule tSL_COMMENT;
private final TerminalRule tESCAPE_JSP;
private final TerminalRule tESCAPE_ORDL;
private final TerminalRule tNUM;
private final TerminalRule tSTR;
@ -3426,6 +3428,8 @@ public class RDLGrammarAccess extends AbstractGrammarElementFinder {
this.tWS = (TerminalRule) GrammarUtil.findRuleForName(getGrammar(), "com.minres.rdl.RDL.WS");
this.tML_COMMENT = (TerminalRule) GrammarUtil.findRuleForName(getGrammar(), "com.minres.rdl.RDL.ML_COMMENT");
this.tSL_COMMENT = (TerminalRule) GrammarUtil.findRuleForName(getGrammar(), "com.minres.rdl.RDL.SL_COMMENT");
this.tESCAPE_JSP = (TerminalRule) GrammarUtil.findRuleForName(getGrammar(), "com.minres.rdl.RDL.ESCAPE_JSP");
this.tESCAPE_ORDL = (TerminalRule) GrammarUtil.findRuleForName(getGrammar(), "com.minres.rdl.RDL.ESCAPE_ORDL");
this.tNUM = (TerminalRule) GrammarUtil.findRuleForName(getGrammar(), "com.minres.rdl.RDL.NUM");
this.tSTR = (TerminalRule) GrammarUtil.findRuleForName(getGrammar(), "com.minres.rdl.RDL.STR");
}
@ -3962,7 +3966,7 @@ public class RDLGrammarAccess extends AbstractGrammarElementFinder {
}
//terminal ML_COMMENT:
// '/*'->'*/' | '<%'->'%>' | '('->')';
// '/*'->'*/';
public TerminalRule getML_COMMENTRule() {
return tML_COMMENT;
}
@ -3973,6 +3977,18 @@ public class RDLGrammarAccess extends AbstractGrammarElementFinder {
return tSL_COMMENT;
}
//terminal ESCAPE_JSP:
// '<%'->'%>';
public TerminalRule getESCAPE_JSPRule() {
return tESCAPE_JSP;
}
//terminal ESCAPE_ORDL:
// '('->')';
public TerminalRule getESCAPE_ORDLRule() {
return tESCAPE_ORDL;
}
//terminal NUM returns ecore::EJavaObject: // <= verilog like numbers with size and base (16'123 'h1fff, ...====================================================================================> <= hexa decimal numbers =============> <numbers>
////'0'..'9'* '\'' ( 'b' ('0' | '1' | '_')+ | 'd'? ('0'..'9' | '_')+ | 'o' ('0'..'7' | '_')+ | 'h' ('0'..'9' | 'a'..'f' | 'A'..'F' | '_')+) | "0x" ('0'..'9' | 'a'..'f' | 'A'..'F')+ | '0'..'9'+;
// '0'..'9'+ '\'b' ('0' | '1' | '_')+ | '0'..'9'+ '\'o' ('0'..'7' | '_')+ | '0'..'9'+ '\'h' ('0'..'9' | 'a'..'f' |