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Code Issues 1 Packages Releases Wiki Activity

Fixed size calculation and error generating std::array of plain

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datatypes
This commit is contained in:
Eyck Jentzsch
2017-10-04 10:10:36 +02:00
parent f950322d05
commit 0e526f811a
6 changed files with 194 additions and 79 deletions
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14
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/AddrmapGenerator.xtend
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@ -3,7 +3,6 @@ package com.minres.rdl.generator
import com.minres.rdl.generator.RdlBaseGenerator
import com.minres.rdl.rdl.ComponentDefinition
import com.minres.rdl.IntegerWithRadix
import com.minres.rdl.rdl.Instantiation
import com.minres.rdl.rdl.ComponentDefinitionType
class AddrmapGenerator extends RdlBaseGenerator {
@ -21,7 +20,7 @@ class AddrmapGenerator extends RdlBaseGenerator {
const std::array<sysc::target_memory_map_entry<32>, «componentDefinition.instanceCount(ComponentDefinitionType.REGFILE)»> e300_plat_map = {{
«FOR instantiation : componentDefinition.instantiationsOfType(ComponentDefinitionType.REGFILE)»
«FOR instance : instantiation.componentInstances»
{&i_«instance.name», 0x«Long.toHexString((instance.address as IntegerWithRadix).value)», 0x«Long.toHexString(instantiation.occupiedSize)»},
{&i_«instance.name», 0x«Long.toHexString((instance.address as IntegerWithRadix).value)», 0x«Long.toHexString(instantiation.byteSize)»},
«ENDFOR»
«ENDFOR»
}};
@ -34,16 +33,5 @@ class AddrmapGenerator extends RdlBaseGenerator {
''
}
def int instanceCount(ComponentDefinition definition, ComponentDefinitionType type){
definition.instantiationsOfType(type).map[it.componentInstances.size].reduce[p1, p2| p1+p2]
}
def instantiationsOfType(ComponentDefinition definition, ComponentDefinitionType type){
definition.instantiations.filter[it.definingComponent.type == type]
}
def long occupiedSize(Instantiation instantiation){
return 4096
}
}

57
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlBaseGenerator.xtend
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@ -13,7 +13,8 @@ import com.minres.rdl.rdl.InstancePropertyRef
import com.minres.rdl.rdl.ComponentDefinitionType
abstract class RdlBaseGenerator {
def long accessWidth(ComponentDefinition definition){
def long accessWidth(ComponentDefinition definition){
var size = 32L
val pa = definition.propertyAssignments.findFirst[PropertyAssignment pa |
pa instanceof ExplicitPropertyAssignment && (pa as ExplicitPropertyAssignment).name==PropertyEnum.ACCESSWIDTH
@ -24,7 +25,19 @@ abstract class RdlBaseGenerator {
}
return size
}
def long regWidth(ComponentDefinition definition){
var size = 32L
val pa = definition.propertyAssignments.findFirst[PropertyAssignment pa |
pa instanceof ExplicitPropertyAssignment && (pa as ExplicitPropertyAssignment).name==PropertyEnum.REGWIDTH
]
if(pa !== null){
val sz = new IntegerWithRadix((pa as ExplicitPropertyAssignment).rhs.effectiveValue)
size=sz.value
}
return size
}
def long getSize(Instantiation instantiation){
val componentDef= instantiation.definingComponent
switch (componentDef.type) {
@ -87,13 +100,51 @@ abstract class RdlBaseGenerator {
}
def String effectiveValue(InstancePropertyRef ref){
throw new RuntimeException()
}
def ComponentDefinition definingComponent(Instantiation instantiation){
if(instantiation.componentRef!==null) instantiation.componentRef else instantiation.component
}
def int instanceCount(ComponentDefinition definition, ComponentDefinitionType type){
definition.instantiationsOfType(type).map[it.componentInstances.size].reduce[p1, p2| p1+p2]
}
def instantiationsOfType(ComponentDefinition definition, ComponentDefinitionType type){
definition.instantiations.filter[it.definingComponent.type == type]
}
def long byteSize(Instantiation instantiation, long start){
val componentDefinition = instantiation.definingComponent
var long componentSize=0;
if(instantiation.definingComponent.type == ComponentDefinitionType.REG){
componentSize=instantiation.definingComponent.regWidth/8
} else
for(subInstantiation: componentDefinition.instantiations)
componentSize = subInstantiation.byteSize(componentSize)
var long lastTopAddress = start
var long topAddress=start
for(componentInstance: instantiation.componentInstances ){
val byteSize = if(componentInstance.address !== null) (componentInstance.address as IntegerWithRadix).value+componentSize else componentSize + lastTopAddress
topAddress = Math.max(topAddress, byteSize)
lastTopAddress = byteSize
}
return topAddress
}
def long byteSize(Instantiation instantiation){
val componentDefinition = instantiation.definingComponent
var long componentSize=0;
if(instantiation.definingComponent.type == ComponentDefinitionType.REG){
componentSize=instantiation.definingComponent.regWidth/8
} else
for(subInstantiation: componentDefinition.instantiations)
componentSize = subInstantiation.byteSize(componentSize)
return componentSize
}
def String generateHeader()
def String generateSource()

6
com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RegfileGenerator.xtend
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@ -81,7 +81,9 @@ class RegfileGenerator extends RdlBaseGenerator{
«ENDIF»
«IF instantiation.component !== null && instantiation.component.type == ComponentDefinitionType.REG»
«IF instantiation.isFilledByField»
uint«instantiation.size»_t «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
«IF instantiation.componentInstances.filter[it.range===null].size>0»
uint«instantiation.size»_t «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
«ENDIF»
«FOR componentInstance : instantiation.componentInstances.filter[it.range!==null]»
std::array<uint«instantiation.size»_t, «componentInstance.range.absSize»> r_«componentInstance.name»;
«ENDFOR»
@ -110,7 +112,7 @@ class RegfileGenerator extends RdlBaseGenerator{
«ENDIF»
«IF instance.range!==null»
«IF instantiation.isFilledByField»
sysc::sc_register_indexed<«instantiation.size»_t, «instance.range.absSize»> «instance.name»;
sysc::sc_register_indexed<uint«instantiation.size»_t, «instance.range.absSize»> «instance.name»;
«ENDIF»
«IF !instantiation.isFilledByField»
sysc::sc_register_indexed<«instantiation.component.effectiveName»_t, «instance.range.absSize»> «instance.name»;