TGFS/TGC-ISS
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splits 32 and 64 bits, disables RVE for now

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Eyck-Alexander Jentzsch 2024-07-11 12:41:14 +02:00
parent 45e5ab6133
commit c4a746d4c8
1 changed files with 7 additions and 2 deletions
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9
Jenkinsfile vendored
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@ -36,11 +36,16 @@ pipeline {
stage("Generate cores and build TGC-ISS"){
steps {
sh '''
for core in TGC5A TGC5B TGC5D TGC5E TGC6B TGC6C TGC6D TGC6E; do
for core in TGC5B TGC5D TGC5E; do #TGC5A
for backend in interp llvm tcc asmjit; do
TGC-GEN/scripts/generate_iss.sh -o dbt-rise-tgc/ -c $core -b ${backend} TGC-GEN/CoreDSL/${core}.core_desc
done
done
for core in TGC6B TGC6C TGC6D TGC6E; do
for backend in interp llvm asmjit; do
TGC-GEN/scripts/generate_iss.sh -o dbt-rise-tgc/ -c $core -b ${backend} TGC-GEN/CoreDSL/${core}.core_desc
done
done
'''
sh 'conan profile new default --detect --force'
sh 'cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DWITH_ASMJIT=ON -DWITH_TCC=ON -DWITH_LLVM=ON'
@ -62,7 +67,7 @@ pipeline {
axes {
axis {
name 'CORE'
values 'TGC5A', 'TGC5B', 'TGC5C', 'TGC5D', 'TGC5E'
values 'TGC5B', 'TGC5C', 'TGC5D', 'TGC5E' // TGC5A
}
axis {
name 'BACKEND'